Hi,
On Fri, Jun 24, 2016 at 7:54 AM, Odzioba, Lukasz
wrote:
> On Tuesday, June 21, 2016 11:38 AM, Peter Zijlstra wrote:
>> Yes, that is the intent, but how is this achieved? I'm not sure I see
>> how the patch ensure this.
>
> If you are confused, then it is likely that I did something wrong here
On Tuesday, June 21, 2016 11:38 AM, Peter Zijlstra wrote:
> Yes, that is the intent, but how is this achieved? I'm not sure I see
> how the patch ensure this.
If you are confused, then it is likely that I did something wrong here.
Let me explain myself.
We already have a mechanism to create stati
On Mon, Jun 20, 2016 at 10:26:30AM +, Odzioba, Lukasz wrote:
> On 08.06.2016 Peter Zijlstra wrote:
> > How does this work in the light of intel_alt_er() ?
>
> Hi Peter,
>
> If the constrained bit is valid on only one of the OCR MSRs (like in case of
> KNL),
> then OCR valid mask will forbid
On 08.06.2016 Peter Zijlstra wrote:
> How does this work in the light of intel_alt_er() ?
Hi Peter,
If the constrained bit is valid on only one of the OCR MSRs (like in case of
KNL),
then OCR valid mask will forbid altering it by the other MSR in intel_alt_er.
If constrained bit is valid on bo
On Wed, Jun 08, 2016 at 06:02:16AM +0200, Lukasz Odzioba wrote:
> For Knights Landing processor we need to filter OFFCORE_RESPONSE
> events by config1 parameter to make sure that it will end up in
> an appropriate PMC to meet specification.
>
> On Knights Landing:
> MSR_OFFCORE_RSP_1 bits 8, 11, 1
For Knights Landing processor we need to filter OFFCORE_RESPONSE
events by config1 parameter to make sure that it will end up in
an appropriate PMC to meet specification.
On Knights Landing:
MSR_OFFCORE_RSP_1 bits 8, 11, 14 can be used only on PMC1
MSR_OFFCORE_RSP_0 bit 38 can be used only on PMC0
6 matches
Mail list logo
