Quoting Alexandru Ardelean (2020-12-02 23:40:36)
> Up until the these limits were global/hard-coded, since they are typically
> limits of the fabric.
>
> However, since this is an FPGA generated clock, this may run on setups
> where one clock is on a fabric, and another one synthesized on another
Up until the these limits were global/hard-coded, since they are typically
limits of the fabric.
However, since this is an FPGA generated clock, this may run on setups
where one clock is on a fabric, and another one synthesized on another
fabric connected via PCIe (or some other inter-connect,
Hi Alex,
On Wed, Dec 02, 2020 at 06:10:42PM +0200, Alexandru Ardelean wrote:
> On Mon, Oct 19, 2020 at 2:14 PM Alexandru Ardelean
> wrote:
> >
> > Up until now the these limits were global/hard-coded, since they are
> > typically limits of the fabric.
> >
> > However, since this is an FPGA
On Mon, Oct 19, 2020 at 2:14 PM Alexandru Ardelean
wrote:
>
> Up until now the these limits were global/hard-coded, since they are
> typically limits of the fabric.
>
> However, since this is an FPGA generated clock, this may run on setups
> where one clock is on a fabric, and another one
Up until now the these limits were global/hard-coded, since they are
typically limits of the fabric.
However, since this is an FPGA generated clock, this may run on setups
where one clock is on a fabric, and another one synthesized on another
fabric connected via PCIe (or some other
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