Re: [RESEND PATCH 1/2] clk: axi-clkgen: wrap limits in a struct and keep copy on the state object

Quoting Alexandru Ardelean (2020-12-02 23:40:36) > Up until the these limits were global/hard-coded, since they are typically > limits of the fabric. > > However, since this is an FPGA generated clock, this may run on setups > where one clock is on a fabric, and another one synthesized on another

[RESEND PATCH 1/2] clk: axi-clkgen: wrap limits in a struct and keep copy on the state object

Up until the these limits were global/hard-coded, since they are typically limits of the fabric. However, since this is an FPGA generated clock, this may run on setups where one clock is on a fabric, and another one synthesized on another fabric connected via PCIe (or some other inter-connect,

Re: [PATCH 1/2] clk: axi-clkgen: wrap limits in a struct and keep copy on the state object

Hi Alex, On Wed, Dec 02, 2020 at 06:10:42PM +0200, Alexandru Ardelean wrote: > On Mon, Oct 19, 2020 at 2:14 PM Alexandru Ardelean > wrote: > > > > Up until now the these limits were global/hard-coded, since they are > > typically limits of the fabric. > > > > However, since this is an FPGA

Re: [PATCH 1/2] clk: axi-clkgen: wrap limits in a struct and keep copy on the state object

On Mon, Oct 19, 2020 at 2:14 PM Alexandru Ardelean wrote: > > Up until now the these limits were global/hard-coded, since they are > typically limits of the fabric. > > However, since this is an FPGA generated clock, this may run on setups > where one clock is on a fabric, and another one

[PATCH 1/2] clk: axi-clkgen: wrap limits in a struct and keep copy on the state object

Up until now the these limits were global/hard-coded, since they are typically limits of the fabric. However, since this is an FPGA generated clock, this may run on setups where one clock is on a fabric, and another one synthesized on another fabric connected via PCIe (or some other