Re: [PATCH 1/2] clk: bcm2835: Support for clock parent selection

Remi Pommarel writes: > Hi, > > On Wed, Nov 04, 2015 at 06:03:31PM -0800, Eric Anholt wrote: > > [...] > >> >> It looks like you've dropped the use of the divisor off of the PLL >> channel when setting a rate. That seems bad for all the other clocks in >> the system, and a feature we couldn't l

Re: [PATCH 1/2] clk: bcm2835: Support for clock parent selection

Hi, On Wed, Nov 04, 2015 at 06:03:31PM -0800, Eric Anholt wrote: [...] > > It looks like you've dropped the use of the divisor off of the PLL > channel when setting a rate. That seems bad for all the other clocks in > the system, and a feature we couldn't lose. Sorry, but I'm not sure to unde

Re: [PATCH 1/2] clk: bcm2835: Support for clock parent selection

Remi Pommarel writes: > Some bcm2835 clocks used by hardware (like "PWM" or "H264") can have multiple > parents. These clocks divide the rate of one parent which can be selected by > setting the proper bits in their clock control register. > > Previously all these parents where handled by a mux c

[PATCH 1/2] clk: bcm2835: Support for clock parent selection

Some bcm2835 clocks used by hardware (like "PWM" or "H264") can have multiple parents. These clocks divide the rate of one parent which can be selected by setting the proper bits in their clock control register. Previously all these parents where handled by a mux clock. But a mux clock cannot be u