On 31/01/19 7:09 PM, Bartosz Golaszewski wrote:
> From: Bartosz Golaszewski
>
> I've been unable to figure out exactly why, but it seems that the
> IRQ_TINT1_TINT34 interrupt for timer 1 needs to be handled as a
> level irq, not edge like all others.
Not sure of the history myself. This has been
On 1/31/19 7:39 AM, Bartosz Golaszewski wrote:
From: Bartosz Golaszewski
I've been unable to figure out exactly why, but it seems that the
IRQ_TINT1_TINT34 interrupt for timer 1 needs to be handled as a
level irq, not edge like all others.
This timer is used by the dsp on dm64* boards only.
L
From: Bartosz Golaszewski
I've been unable to figure out exactly why, but it seems that the
IRQ_TINT1_TINT34 interrupt for timer 1 needs to be handled as a
level irq, not edge like all others.
This timer is used by the dsp on dm64* boards only.
Let's move the handler setup out of the aintc driv
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