> From: Andrew Murray
>
> On Tue, Sep 10, 2019 at 09:51:41PM +0530, Pankaj Dubey wrote:
> > On Tue, 10 Sep 2019 at 19:59, Andrew Murray
> wrote:
> > >
> > > On Tue, Sep 10, 2019 at 05:55:02PM +0530, Pankaj Dubey wrote:
> > > > From: Anvesh Salveru
> > > >
> > > > In some platforms, PCIe PHY
On Tue, Sep 10, 2019 at 09:51:41PM +0530, Pankaj Dubey wrote:
> On Tue, 10 Sep 2019 at 19:59, Andrew Murray wrote:
> >
> > On Tue, Sep 10, 2019 at 05:55:02PM +0530, Pankaj Dubey wrote:
> > > From: Anvesh Salveru
> > >
> > > In some platforms, PCIe PHY may have issues which will prevent linkup
> >
On Tue, 10 Sep 2019 at 19:59, Andrew Murray wrote:
>
> On Tue, Sep 10, 2019 at 05:55:02PM +0530, Pankaj Dubey wrote:
> > From: Anvesh Salveru
> >
> > In some platforms, PCIe PHY may have issues which will prevent linkup
> > to happen in GEN3 or high speed. In case equalization fails, link will
>
On Tue, Sep 10, 2019 at 05:55:02PM +0530, Pankaj Dubey wrote:
> From: Anvesh Salveru
>
> In some platforms, PCIe PHY may have issues which will prevent linkup
> to happen in GEN3 or high speed. In case equalization fails, link will
> fallback to GEN1.
>
> Designware controller gives flexibility
From: Anvesh Salveru
In some platforms, PCIe PHY may have issues which will prevent linkup
to happen in GEN3 or high speed. In case equalization fails, link will
fallback to GEN1.
Designware controller gives flexibility to disable GEN3 equalization
completely or only phase 2 and 3.
Platform dri
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