On 06/01, Andy Tang wrote:
> Hi Stephen,
>
> Thanks for your applying.
>
> There are other two patches sent on April 6, 2017:
> https://patchwork.kernel.org/patch/9665973/
> https://patchwork.kernel.org/patch/9665977/
>
> Hope they are in your review queue. Please give it a review.
>
Yep
On 06/01, Andy Tang wrote:
> Hi Stephen,
>
> Thanks for your applying.
>
> There are other two patches sent on April 6, 2017:
> https://patchwork.kernel.org/patch/9665973/
> https://patchwork.kernel.org/patch/9665977/
>
> Hope they are in your review queue. Please give it a review.
>
Yep
rm-ker...@lists.infradead.org; Scott Wood
<o...@buserror.net>
Subject: Re: [PATCH 2/2 v2] clk: qoriq: Separate root input clock for core PLLs
on ls1012a
On 03/20, Yuantian Tang wrote:
> From: Scott Wood <o...@buserror.net>
>
> ls1012a has separate input root clocks for core PLLs versus the
>
Subject: Re: [PATCH 2/2 v2] clk: qoriq: Separate root input clock for core PLLs
on ls1012a
On 03/20, Yuantian Tang wrote:
> From: Scott Wood
>
> ls1012a has separate input root clocks for core PLLs versus the
> platform PLL, with the latter described as sysclk in the hw docs.
> If
On 03/20, Yuantian Tang wrote:
> From: Scott Wood
>
> ls1012a has separate input root clocks for core PLLs versus the
> platform PLL, with the latter described as sysclk in the hw docs.
> If a second input clock, named "coreclk", is present, this clock will be
> used for the
On 03/20, Yuantian Tang wrote:
> From: Scott Wood
>
> ls1012a has separate input root clocks for core PLLs versus the
> platform PLL, with the latter described as sysclk in the hw docs.
> If a second input clock, named "coreclk", is present, this clock will be
> used for the core PLLs.
>
>
From: Scott Wood
ls1012a has separate input root clocks for core PLLs versus the
platform PLL, with the latter described as sysclk in the hw docs.
If a second input clock, named "coreclk", is present, this clock will be
used for the core PLLs.
Signed-off-by: Scott Wood
From: Scott Wood
ls1012a has separate input root clocks for core PLLs versus the
platform PLL, with the latter described as sysclk in the hw docs.
If a second input clock, named "coreclk", is present, this clock will be
used for the core PLLs.
Signed-off-by: Scott Wood
Signed-off-by: Tang
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