Re: [PATCH 3/5] clk: ingenic: Don't use CLK_SET_RATE_GATE for PLL

Quoting Paul Cercueil (2020-09-02 18:50:46) > CLK_SET_RATE_GATE means that the clock must be gated when being > reclocked. This is not the case for the PLLs in Ingenic SoCs. > > Signed-off-by: Paul Cercueil > --- Applied to clk-next

[PATCH 3/5] clk: ingenic: Don't use CLK_SET_RATE_GATE for PLL

CLK_SET_RATE_GATE means that the clock must be gated when being reclocked. This is not the case for the PLLs in Ingenic SoCs. Signed-off-by: Paul Cercueil --- drivers/clk/ingenic/cgu.c | 9 +++-- 1 file changed, 7 insertions(+), 2 deletions(-) diff --git a/drivers/clk/ingenic/cgu.c