Re: [PATCH 7/7] MIPS: SGI-IP27: abstract chipset irq from bridge

On Mon, 28 Jan 2019 08:27:21 -0800 Christoph Hellwig wrote: > On Mon, Jan 28, 2019 at 03:01:35PM +0100, Thomas Bogendoerfer wrote: > > On Mon, 28 Jan 2019 05:33:17 -0800 > > Christoph Hellwig wrote: > > > > > Shouldnt this just use chained irqchip drivers instead? > > > > you mean using

Re: [PATCH 7/7] MIPS: SGI-IP27: abstract chipset irq from bridge

On Mon, Jan 28, 2019 at 03:01:35PM +0100, Thomas Bogendoerfer wrote: > On Mon, 28 Jan 2019 05:33:17 -0800 > Christoph Hellwig wrote: > > > Shouldnt this just use chained irqchip drivers instead? > > you mean using irq_set_chained_handler() ? If yes, this IMHO doesn't look > usefull > because

Re: [PATCH 7/7] MIPS: SGI-IP27: abstract chipset irq from bridge

On Mon, 28 Jan 2019 05:33:17 -0800 Christoph Hellwig wrote: > Shouldnt this just use chained irqchip drivers instead? you mean using irq_set_chained_handler() ? If yes, this IMHO doesn't look usefull because it's used for adding a secondary interrupt controller. But what I need is telling

Re: [PATCH 7/7] MIPS: SGI-IP27: abstract chipset irq from bridge

Shouldnt this just use chained irqchip drivers instead?

[PATCH 7/7] MIPS: SGI-IP27: abstract chipset irq from bridge

Bridge ASIC is widely used in different SGI systems, but the connected chipset is either HUB, HEART or BEDROCK. This commit abstracts chipset irq setup and moves the bridge related irq setup to bridge code. Signed-off-by: Thomas Bogendoerfer --- arch/mips/include/asm/pci/bridge.h| 2 -