Dear Sebastian,
On Mon, 21 Sep 2015 10:18:25 +0800
Jisheng Zhang wrote:
> Dear Sebastian,
>
> On Sun, 20 Sep 2015 20:04:01 +0200
> Sebastian Hesselbarth wrote:
>
> > On 14.09.2015 08:47, Jisheng Zhang wrote:
> > > In Berlin SoCs, there are two kinds of cpu reset control registers: the
> > >
Dear Sebastian,
On Mon, 21 Sep 2015 10:18:25 +0800
Jisheng Zhang wrote:
> Dear Sebastian,
>
> On Sun, 20 Sep 2015 20:04:01 +0200
> Sebastian Hesselbarth wrote:
>
> > On 14.09.2015 08:47, Jisheng Zhang wrote:
> > > In Berlin SoCs, there
Dear Sebastian,
On Sun, 20 Sep 2015 20:04:01 +0200
Sebastian Hesselbarth wrote:
> On 14.09.2015 08:47, Jisheng Zhang wrote:
> > In Berlin SoCs, there are two kinds of cpu reset control registers: the
> > first one's corresponding bits will be self-cleared after some cycles,
> > while the second
On 14.09.2015 08:47, Jisheng Zhang wrote:
In Berlin SoCs, there are two kinds of cpu reset control registers: the
first one's corresponding bits will be self-cleared after some cycles,
while the second one's bits won't. Previously the first kind of reset
control register is used, this patch uses
Dear Sebastian,
On Sun, 20 Sep 2015 20:04:01 +0200
Sebastian Hesselbarth wrote:
> On 14.09.2015 08:47, Jisheng Zhang wrote:
> > In Berlin SoCs, there are two kinds of cpu reset control registers: the
> > first one's corresponding bits will be self-cleared after
On 14.09.2015 08:47, Jisheng Zhang wrote:
In Berlin SoCs, there are two kinds of cpu reset control registers: the
first one's corresponding bits will be self-cleared after some cycles,
while the second one's bits won't. Previously the first kind of reset
control register is used, this patch uses
In Berlin SoCs, there are two kinds of cpu reset control registers: the
first one's corresponding bits will be self-cleared after some cycles,
while the second one's bits won't. Previously the first kind of reset
control register is used, this patch uses the second kind one to prepare
for the next
In Berlin SoCs, there are two kinds of cpu reset control registers: the
first one's corresponding bits will be self-cleared after some cycles,
while the second one's bits won't. Previously the first kind of reset
control register is used, this patch uses the second kind one to prepare
for the next
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