Quoting A.s. Dong (2018-11-14 05:01:43)
> pllv4 is designed for System Clock Generation (SCG) module observed
> in IMX ULP SoC series. e.g. i.MX7ULP.
>
> The SCG modules generates clock used to derive processor, system,
> peripheral bus and external memory interface clocks while this patch
> inten
pllv4 is designed for System Clock Generation (SCG) module observed
in IMX ULP SoC series. e.g. i.MX7ULP.
The SCG modules generates clock used to derive processor, system,
peripheral bus and external memory interface clocks while this patch
intends to support the PLL part.
Cc: Stephen Boyd
Cc: M
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