On Wed, 2016-04-13 at 17:48 +0300, Andy Shevchenko wrote:
> Wait, you mean flow control between DMA controller and UART FIFO, or
> I
> misread you?
Yup.
It's a while since I read the spec and talked to the relevant people
but... I have this memory that the FIFO fill signal and DMA block were
'wir
On Wed, 2016-04-13 at 15:34 +0100, Bryan O'Donoghue wrote:
> On Wed, 2016-04-13 at 15:03 +0300, Andy Shevchenko wrote:
> >
> > Because a probability of FIFO overrun.
> >
> > There is a big chapter ("Peripheral Burst Transaction Requests") in
> > dw_apb_dmac_db.pdf covering this.
> I thought there
On Wed, 2016-04-13 at 15:03 +0300, Andy Shevchenko wrote:
> Because a probability of FIFO overrun.
>
> There is a big chapter ("Peripheral Burst Transaction Requests") in
> dw_apb_dmac_db.pdf covering this.
I thought there was flow control between the controller and the FIFO
here ? I don't have t
On Wed, 2016-04-13 at 12:22 +0100, Bryan O'Donoghue wrote:
> On Tue, 2016-04-12 at 19:50 +0300, Andy Shevchenko wrote:
> >
> > >
> > > I haven't read your V2 yet but on this, I'd suggest raising the
> > burst
> > >
> > > size to 32 bytes for UART (no higher) we found during bringup that
> > > la
On Tue, 2016-04-12 at 19:50 +0300, Andy Shevchenko wrote:
> > I haven't read your V2 yet but on this, I'd suggest raising the
> burst
> > size to 32 bytes for UART (no higher) we found during bringup that
> > larger sizes "fall-over and die" but, anything up to 32 bytes is OK
> -
> > and therefore
On Tue, 2016-04-12 at 17:25 +0100, Bryan O'Donoghue wrote:
> On Mon, 2016-04-11 at 18:51 +0300, Andy Shevchenko wrote:
> >
> > On Mon, Apr 11, 2016 at 6:33 PM, Bryan O'Donoghue
> > wrote:
> > >
> > > On Thu, 2016-04-07 at 23:37 +0300, Andy Shevchenko wrote:
> > >
> > > Preface. I tried this on
On Mon, 2016-04-11 at 18:51 +0300, Andy Shevchenko wrote:
> On Mon, Apr 11, 2016 at 6:33 PM, Bryan O'Donoghue
> wrote:
> > On Thu, 2016-04-07 at 23:37 +0300, Andy Shevchenko wrote:
> >
> > Preface. I tried this on Galileo and it appears to work. I'll do
> > some
> > throughput testing to verify b
On Mon, Apr 11, 2016 at 6:51 PM, Andy Shevchenko
wrote:
> On Mon, Apr 11, 2016 at 6:33 PM, Bryan O'Donoghue
> wrote:
>> On Thu, 2016-04-07 at 23:37 +0300, Andy Shevchenko wrote:
>>
>> Preface. I tried this on Galileo and it appears to work. I'll do some
>> throughput testing to verify but, initia
On Mon, Apr 11, 2016 at 6:33 PM, Bryan O'Donoghue
wrote:
> On Thu, 2016-04-07 at 23:37 +0300, Andy Shevchenko wrote:
>
> Preface. I tried this on Galileo and it appears to work. I'll do some
> throughput testing to verify but, initially the results are positive :)
I submitted (and pushed into my
On Thu, 2016-04-07 at 23:37 +0300, Andy Shevchenko wrote:
Preface. I tried this on Galileo and it appears to work. I'll do some
throughput testing to verify but, initially the results are positive :)
> + lpss->dma_maxburst = 8;
Are these dwords ? If those are bytes then the maxburst value
DMA on Intel Quark SoC is a part of UART IP block. Enable it.
Signed-off-by: Andy Shevchenko
---
drivers/tty/serial/8250/8250_lpss.c | 60 +++--
1 file changed, 57 insertions(+), 3 deletions(-)
diff --git a/drivers/tty/serial/8250/8250_lpss.c
b/drivers/tty/seria
11 matches
Mail list logo
