On 5/15/2014 12:23 PM, Arnd Bergmann wrote:
On Thursday 15 May 2014 12:01:32 Murali Karicheri wrote:
+static int
+keystone_pcie_fault(unsigned long addr, unsigned int fsr,
+ struct pt_regs *regs)
+{
+ unsigned long instr = *(unsigned long *) instruction_pointer(regs);
+
+
On 5/15/2014 12:23 PM, Arnd Bergmann wrote:
On Thursday 15 May 2014 12:01:32 Murali Karicheri wrote:
+static int
+keystone_pcie_fault(unsigned long addr, unsigned int fsr,
+ struct pt_regs *regs)
+{
+ unsigned long instr = *(unsigned long *) instruction_pointer(regs);
+
+
On Thu, May 22, 2014 at 06:20:19PM -0400, Murali Karicheri wrote:
>> What is the MPSS?
>
>MPS published in DEV CAP is 1 (256 bytes). In our IP for some reason,
>mrss is set to 2 though IP
>support only 256 bytes. I am trying to resolve this with IP team. If
>this is an IP issue,
On Thu, May 22, 2014 at 06:20:19PM -0400, Murali Karicheri wrote:
What is the MPSS?
MPS published in DEV CAP is 1 (256 bytes). In our IP for some reason,
mrss is set to 2 though IP
support only 256 bytes. I am trying to resolve this with IP team. If
this is an IP issue, then
On Wed, May 21, 2014 at 07:32:58PM -0400, Murali Karicheri wrote:
> >Not quite, it first scans the network checking the Maximum Payload Size
> >Supported (MPSS) for each device, and chooses the highest supported by
> >all as the MPS for all.
> Why highest? It should be lowest so that all on the
On 5/20/2014 1:02 PM, Jason Gunthorpe wrote:
On Fri, May 16, 2014 at 08:29:56PM +, Karicheri, Muralidharan wrote:
But pcie_bus_configure_settings just make sure the mrrs for a device
is not greater than the max payload size.
Not quite, it first scans the network checking the Maximum
On 5/20/2014 1:02 PM, Jason Gunthorpe wrote:
On Fri, May 16, 2014 at 08:29:56PM +, Karicheri, Muralidharan wrote:
But pcie_bus_configure_settings just make sure the mrrs for a device
is not greater than the max payload size.
Not quite, it first scans the network checking the Maximum
On Wed, May 21, 2014 at 07:32:58PM -0400, Murali Karicheri wrote:
Not quite, it first scans the network checking the Maximum Payload Size
Supported (MPSS) for each device, and chooses the highest supported by
all as the MPS for all.
Why highest? It should be lowest so that all on the bus can
On Tue, May 20, 2014 at 11:22:22AM -0600, Bjorn Helgaas wrote:
> On Tue, May 20, 2014 at 11:02 AM, Jason Gunthorpe
> wrote:
> > On Fri, May 16, 2014 at 08:29:56PM +, Karicheri, Muralidharan wrote:
> >
> >> But pcie_bus_configure_settings just make sure the mrrs for a device
> >> is not
On Tue, May 20, 2014 at 11:02 AM, Jason Gunthorpe
wrote:
> On Fri, May 16, 2014 at 08:29:56PM +, Karicheri, Muralidharan wrote:
>
>> But pcie_bus_configure_settings just make sure the mrrs for a device
>> is not greater than the max payload size.
>
> Not quite, it first scans the network
On Tue, May 20, 2014 at 1:55 AM, Arnd Bergmann wrote:
> On Monday 19 May 2014 17:10:50 Murali Karicheri wrote:
>> On ARM, by default pci_bus_config seems to be set to 0
>> (PCIE_BUS_TUNE_OFF). So the code doesn't get
>> executed for this default. But for PCIE_BUS_SAFE, it doesn't change the
>>
On Fri, May 16, 2014 at 08:29:56PM +, Karicheri, Muralidharan wrote:
> But pcie_bus_configure_settings just make sure the mrrs for a device
> is not greater than the max payload size.
Not quite, it first scans the network checking the Maximum Payload Size
Supported (MPSS) for each device,
On Monday 19 May 2014 17:10:50 Murali Karicheri wrote:
> On 5/19/2014 8:06 AM, Arnd Bergmann wrote:
> > On Friday 16 May 2014 16:26:51 Murali Karicheri wrote:
> >> On 5/15/2014 2:20 PM, Arnd Bergmann wrote:
> >>> On Thursday 15 May 2014 13:45:08 Murali Karicheri wrote:
> >> +#ifdef
On Monday 19 May 2014 17:10:50 Murali Karicheri wrote:
On 5/19/2014 8:06 AM, Arnd Bergmann wrote:
On Friday 16 May 2014 16:26:51 Murali Karicheri wrote:
On 5/15/2014 2:20 PM, Arnd Bergmann wrote:
On Thursday 15 May 2014 13:45:08 Murali Karicheri wrote:
+#ifdef CONFIG_PCI_KEYSTONE
+/*
On Fri, May 16, 2014 at 08:29:56PM +, Karicheri, Muralidharan wrote:
But pcie_bus_configure_settings just make sure the mrrs for a device
is not greater than the max payload size.
Not quite, it first scans the network checking the Maximum Payload Size
Supported (MPSS) for each device, and
On Tue, May 20, 2014 at 1:55 AM, Arnd Bergmann a...@arndb.de wrote:
On Monday 19 May 2014 17:10:50 Murali Karicheri wrote:
On ARM, by default pci_bus_config seems to be set to 0
(PCIE_BUS_TUNE_OFF). So the code doesn't get
executed for this default. But for PCIE_BUS_SAFE, it doesn't change
On Tue, May 20, 2014 at 11:02 AM, Jason Gunthorpe
jguntho...@obsidianresearch.com wrote:
On Fri, May 16, 2014 at 08:29:56PM +, Karicheri, Muralidharan wrote:
But pcie_bus_configure_settings just make sure the mrrs for a device
is not greater than the max payload size.
Not quite, it first
On Tue, May 20, 2014 at 11:22:22AM -0600, Bjorn Helgaas wrote:
On Tue, May 20, 2014 at 11:02 AM, Jason Gunthorpe
jguntho...@obsidianresearch.com wrote:
On Fri, May 16, 2014 at 08:29:56PM +, Karicheri, Muralidharan wrote:
But pcie_bus_configure_settings just make sure the mrrs for a
On 5/19/2014 8:06 AM, Arnd Bergmann wrote:
On Friday 16 May 2014 16:26:51 Murali Karicheri wrote:
On 5/15/2014 2:20 PM, Arnd Bergmann wrote:
On Thursday 15 May 2014 13:45:08 Murali Karicheri wrote:
+#ifdef CONFIG_PCI_KEYSTONE
+/*
+ * The KeyStone PCIe controller has maximum read request size
On Friday 16 May 2014 18:44:44 Murali Karicheri wrote:
> On 5/15/2014 12:28 PM, Arnd Bergmann wrote:
> > On Thursday 15 May 2014 12:01:32 Murali Karicheri wrote:
> >> +Sample bindings shown below:-
> >> +
> >> + - Remove ti,enable-linktrain if boot loader already does Link training
> >> and do EP
On Friday 16 May 2014 16:26:51 Murali Karicheri wrote:
> On 5/15/2014 2:20 PM, Arnd Bergmann wrote:
> > On Thursday 15 May 2014 13:45:08 Murali Karicheri wrote:
> +#ifdef CONFIG_PCI_KEYSTONE
> +/*
> + * The KeyStone PCIe controller has maximum read request size of 256
> bytes.
On Friday 16 May 2014 16:26:51 Murali Karicheri wrote:
On 5/15/2014 2:20 PM, Arnd Bergmann wrote:
On Thursday 15 May 2014 13:45:08 Murali Karicheri wrote:
+#ifdef CONFIG_PCI_KEYSTONE
+/*
+ * The KeyStone PCIe controller has maximum read request size of 256
bytes.
+ */
+static void
On Friday 16 May 2014 18:44:44 Murali Karicheri wrote:
On 5/15/2014 12:28 PM, Arnd Bergmann wrote:
On Thursday 15 May 2014 12:01:32 Murali Karicheri wrote:
+Sample bindings shown below:-
+
+ - Remove ti,enable-linktrain if boot loader already does Link training
and do EP
+
On 5/19/2014 8:06 AM, Arnd Bergmann wrote:
On Friday 16 May 2014 16:26:51 Murali Karicheri wrote:
On 5/15/2014 2:20 PM, Arnd Bergmann wrote:
On Thursday 15 May 2014 13:45:08 Murali Karicheri wrote:
+#ifdef CONFIG_PCI_KEYSTONE
+/*
+ * The KeyStone PCIe controller has maximum read request size
On 5/15/2014 12:28 PM, Arnd Bergmann wrote:
On Thursday 15 May 2014 12:01:32 Murali Karicheri wrote:
+Sample bindings shown below:-
+
+ - Remove ti,enable-linktrain if boot loader already does Link training and do
EP
+ configuration.
+ - Remove ti,init-phy if boot loader already initialize
ar, Santosh; Mohit Kumar; Jingoo Han;
>Bjorn Helgaas;
>Strashko, Grygorii
>Subject: [PATCH v1 5/5] pci: keystone: add pcie driver based on designware
>core driver
>
>keystone pcie hardware is based on designware version 3.65.
>This driver make use of the functions
goo Han; linux-kernel@vger.kernel.org; Shilimkar,
>Santosh; Mohit
>Kumar; Bjorn Helgaas
>Subject: Re: [PATCH v1 5/5] pci: keystone: add pcie driver based on designware
>core
>driver
>
>On Thu, May 15, 2014 at 04:04:47PM -0400, Murali Karicheri wrote:
>
>> Jason What yo
On 5/15/2014 2:20 PM, Arnd Bergmann wrote:
On Thursday 15 May 2014 13:45:08 Murali Karicheri wrote:
+#ifdef CONFIG_PCI_KEYSTONE
+/*
+ * The KeyStone PCIe controller has maximum read request size of 256 bytes.
+ */
+static void quirk_limit_readrequest(struct pci_dev *dev)
+{
+int readrq =
On 5/15/2014 2:20 PM, Arnd Bergmann wrote:
On Thursday 15 May 2014 13:45:08 Murali Karicheri wrote:
+#ifdef CONFIG_PCI_KEYSTONE
+/*
+ * The KeyStone PCIe controller has maximum read request size of 256 bytes.
+ */
+static void quirk_limit_readrequest(struct pci_dev *dev)
+{
+int readrq =
@vger.kernel.org; Shilimkar,
Santosh; Mohit
Kumar; Bjorn Helgaas
Subject: Re: [PATCH v1 5/5] pci: keystone: add pcie driver based on designware
core
driver
On Thu, May 15, 2014 at 04:04:47PM -0400, Murali Karicheri wrote:
Jason What you mean by The PCI core handles setting the maximum read
request size
; Jingoo Han;
Bjorn Helgaas;
Strashko, Grygorii
Subject: [PATCH v1 5/5] pci: keystone: add pcie driver based on designware
core driver
keystone pcie hardware is based on designware version 3.65.
This driver make use of the functions from pci-dw-old.c and pci-dw-old-msi.c
to implement
the driver
On 5/15/2014 12:28 PM, Arnd Bergmann wrote:
On Thursday 15 May 2014 12:01:32 Murali Karicheri wrote:
+Sample bindings shown below:-
+
+ - Remove ti,enable-linktrain if boot loader already does Link training and do
EP
+ configuration.
+ - Remove ti,init-phy if boot loader already initialize
On Thu, May 15, 2014 at 04:04:47PM -0400, Murali Karicheri wrote:
> Jason What you mean by "The PCI core handles setting the maximum
> read request size already" I see there is function pcie_write_mrrs()
> in the drivers/pci/probe.c that reads the mps using pcie_get_mps()
> and then set mrrs to
On 5/15/2014 2:39 PM, Jason Gunthorpe wrote:
On Thu, May 15, 2014 at 08:20:13PM +0200, Arnd Bergmann wrote:
On Thursday 15 May 2014 13:45:08 Murali Karicheri wrote:
+#ifdef CONFIG_PCI_KEYSTONE
+/*
+ * The KeyStone PCIe controller has maximum read request size of 256 bytes.
+ */
+static void
On Thu, May 15, 2014 at 08:20:13PM +0200, Arnd Bergmann wrote:
> On Thursday 15 May 2014 13:45:08 Murali Karicheri wrote:
> > >> +#ifdef CONFIG_PCI_KEYSTONE
> > >> +/*
> > >> + * The KeyStone PCIe controller has maximum read request size of 256
> > >> bytes.
> > >> + */
> > >> +static void
On Thursday 15 May 2014 13:45:08 Murali Karicheri wrote:
> >> +#ifdef CONFIG_PCI_KEYSTONE
> >> +/*
> >> + * The KeyStone PCIe controller has maximum read request size of 256
> >> bytes.
> >> + */
> >> +static void quirk_limit_readrequest(struct pci_dev *dev)
> >> +{
> >> +int readrq =
Arnd,
Thanks for the review. I may have more questions as I digest the
comments. Here is the
immediate one.
+#ifdef CONFIG_PCI_KEYSTONE
+/*
+ * The KeyStone PCIe controller has maximum read request size of 256 bytes.
+ */
+static void quirk_limit_readrequest(struct pci_dev *dev)
+{
+
On Thursday 15 May 2014 12:01:32 Murali Karicheri wrote:
> +Sample bindings shown below:-
> +
> + - Remove ti,enable-linktrain if boot loader already does Link training and
> do EP
> + configuration.
> + - Remove ti,init-phy if boot loader already initialize the phy and sets up
> pcie
> +
On Thursday 15 May 2014 12:01:32 Murali Karicheri wrote:
> +static int
> +keystone_pcie_fault(unsigned long addr, unsigned int fsr,
> + struct pt_regs *regs)
> +{
> + unsigned long instr = *(unsigned long *) instruction_pointer(regs);
> +
> + if ((instr & 0x0e100090) ==
keystone pcie hardware is based on designware version 3.65.
This driver make use of the functions from pci-dw-old.c and
pci-dw-old-msi.c to implement the driver.
Driver mainly handle the platform specific part of the PCI
driver and depends on DW Old driver to configure application
specific
keystone pcie hardware is based on designware version 3.65.
This driver make use of the functions from pci-dw-old.c and
pci-dw-old-msi.c to implement the driver.
Driver mainly handle the platform specific part of the PCI
driver and depends on DW Old driver to configure application
specific
On Thursday 15 May 2014 12:01:32 Murali Karicheri wrote:
+static int
+keystone_pcie_fault(unsigned long addr, unsigned int fsr,
+ struct pt_regs *regs)
+{
+ unsigned long instr = *(unsigned long *) instruction_pointer(regs);
+
+ if ((instr 0x0e100090) == 0x00100090) {
On Thursday 15 May 2014 12:01:32 Murali Karicheri wrote:
+Sample bindings shown below:-
+
+ - Remove ti,enable-linktrain if boot loader already does Link training and
do EP
+ configuration.
+ - Remove ti,init-phy if boot loader already initialize the phy and sets up
pcie
+ link
You
Arnd,
Thanks for the review. I may have more questions as I digest the
comments. Here is the
immediate one.
+#ifdef CONFIG_PCI_KEYSTONE
+/*
+ * The KeyStone PCIe controller has maximum read request size of 256 bytes.
+ */
+static void quirk_limit_readrequest(struct pci_dev *dev)
+{
+
On Thursday 15 May 2014 13:45:08 Murali Karicheri wrote:
+#ifdef CONFIG_PCI_KEYSTONE
+/*
+ * The KeyStone PCIe controller has maximum read request size of 256
bytes.
+ */
+static void quirk_limit_readrequest(struct pci_dev *dev)
+{
+int readrq = pcie_get_readrq(dev);
+
+
On Thu, May 15, 2014 at 08:20:13PM +0200, Arnd Bergmann wrote:
On Thursday 15 May 2014 13:45:08 Murali Karicheri wrote:
+#ifdef CONFIG_PCI_KEYSTONE
+/*
+ * The KeyStone PCIe controller has maximum read request size of 256
bytes.
+ */
+static void quirk_limit_readrequest(struct
On 5/15/2014 2:39 PM, Jason Gunthorpe wrote:
On Thu, May 15, 2014 at 08:20:13PM +0200, Arnd Bergmann wrote:
On Thursday 15 May 2014 13:45:08 Murali Karicheri wrote:
+#ifdef CONFIG_PCI_KEYSTONE
+/*
+ * The KeyStone PCIe controller has maximum read request size of 256 bytes.
+ */
+static void
On Thu, May 15, 2014 at 04:04:47PM -0400, Murali Karicheri wrote:
Jason What you mean by The PCI core handles setting the maximum
read request size already I see there is function pcie_write_mrrs()
in the drivers/pci/probe.c that reads the mps using pcie_get_mps()
and then set mrrs to mps.
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