On Mon, Aug 05, 2019 at 08:03:10AM -0400, Qian Cai wrote:
>
>
> > On Aug 5, 2019, at 6:00 AM, Will Deacon wrote:
> >
> > On Fri, Aug 02, 2019 at 08:33:58PM -0400, Qian Cai wrote:
> >> The commit d5370f754875 ("arm64: prefetch: add alternative pattern for
> >> CPUs without a prefetcher")
> On Aug 5, 2019, at 6:00 AM, Will Deacon wrote:
>
> On Fri, Aug 02, 2019 at 08:33:58PM -0400, Qian Cai wrote:
>> The commit d5370f754875 ("arm64: prefetch: add alternative pattern for
>> CPUs without a prefetcher") introduced MIDR_IS_CPU_MODEL_RANGE() to be
>> used in has_no_hw_prefetch()
On Fri, Aug 02, 2019 at 08:33:58PM -0400, Qian Cai wrote:
> The commit d5370f754875 ("arm64: prefetch: add alternative pattern for
> CPUs without a prefetcher") introduced MIDR_IS_CPU_MODEL_RANGE() to be
> used in has_no_hw_prefetch() with rv_min=0 which generates a compilation
> warning from GCC,
The commit d5370f754875 ("arm64: prefetch: add alternative pattern for
CPUs without a prefetcher") introduced MIDR_IS_CPU_MODEL_RANGE() to be
used in has_no_hw_prefetch() with rv_min=0 which generates a compilation
warning from GCC,
In file included from ./arch/arm64/include/asm/cache.h:8,
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