Re: [PATCH v2 0/7] Tegra210 clock bug fixes

2017-03-20 Thread Thierry Reding
On Thu, Feb 23, 2017 at 12:44:37PM +0200, Peter De Schrijver wrote: > A number of bug fixes for the Tegra210 clock implementation. > > Changelog: > > v2: add better description for 'remove non-existing pll_m_out1 clock' > > Peter De Schrijver (7): > clk: tegra: fix pll_a1 iddq register, add

Re: [PATCH v2 0/7] Tegra210 clock bug fixes

2017-03-20 Thread Thierry Reding
On Thu, Feb 23, 2017 at 12:44:37PM +0200, Peter De Schrijver wrote: > A number of bug fixes for the Tegra210 clock implementation. > > Changelog: > > v2: add better description for 'remove non-existing pll_m_out1 clock' > > Peter De Schrijver (7): > clk: tegra: fix pll_a1 iddq register, add

Re: [PATCH v2 0/7] Tegra210 clock bug fixes

2017-02-27 Thread Mikko Perttunen
Series, Reviewed-by: Mikko Perttunen Tested-by: Mikko Perttunen On 02/23/2017 12:44 PM, Peter De Schrijver wrote: A number of bug fixes for the Tegra210 clock implementation. Changelog: v2: add better description for 'remove non-existing

Re: [PATCH v2 0/7] Tegra210 clock bug fixes

2017-02-27 Thread Mikko Perttunen
Series, Reviewed-by: Mikko Perttunen Tested-by: Mikko Perttunen On 02/23/2017 12:44 PM, Peter De Schrijver wrote: A number of bug fixes for the Tegra210 clock implementation. Changelog: v2: add better description for 'remove non-existing pll_m_out1 clock' Peter De Schrijver (7): clk:

[PATCH v2 0/7] Tegra210 clock bug fixes

2017-02-23 Thread Peter De Schrijver
A number of bug fixes for the Tegra210 clock implementation. Changelog: v2: add better description for 'remove non-existing pll_m_out1 clock' Peter De Schrijver (7): clk: tegra: fix pll_a1 iddq register, add pll_a1 clk: tegra: fix isp clock modelling clk: tegra: correct afi parent clk:

[PATCH v2 0/7] Tegra210 clock bug fixes

2017-02-23 Thread Peter De Schrijver
A number of bug fixes for the Tegra210 clock implementation. Changelog: v2: add better description for 'remove non-existing pll_m_out1 clock' Peter De Schrijver (7): clk: tegra: fix pll_a1 iddq register, add pll_a1 clk: tegra: fix isp clock modelling clk: tegra: correct afi parent clk: