On Mon, Sep 16, 2019 at 02:50:17PM +0200, Neil Armstrong wrote:
> Add PCIE bindings for the Amlogic G12A SoC, the support is the same
> but the PHY is shared with USB3 to control the differential lines.
>
> Thus this adds a phy phandle to control the PHY, and only requires the
> MIPI clock for the
Add PCIE bindings for the Amlogic G12A SoC, the support is the same
but the PHY is shared with USB3 to control the differential lines.
Thus this adds a phy phandle to control the PHY, and only requires the
MIPI clock for the Amlogic AXG SoC Family.
Signed-off-by: Neil Armstrong
Reviewed-by: Rob
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