> How to do this? Should I change the line to
>
> + if (static_branch_unlikely(&rdt_enable_key))?
See Documentation/static-keys.txt, there are some examples.
also "git grep static_branch_unlikely" to see existing users
-Tony
> From: Thomas Gleixner [mailto:t...@linutronix.de]
> Sent: Thursday, September 08, 2016 2:54 AM
>
> On Thu, 8 Sep 2016, Fenghua Yu wrote:
> > +extern struct static_key rdt_enable_key; void
> > +__intel_rdt_sched_in(void *dummy);
> > +
> > struct clos_cbm_table {
> > unsigned long cbm;
> >
On 8 September 2016 at 04:57, Fenghua Yu wrote:
> diff --git a/arch/x86/kernel/cpu/intel_rdt.c b/arch/x86/kernel/cpu/intel_rdt.c
> index 9cf3a7d..9f30492 100644
> --- a/arch/x86/kernel/cpu/intel_rdt.c
> +++ b/arch/x86/kernel/cpu/intel_rdt.c
> @@ -21,6 +21,8 @@
> */
> #include
> #include
> +#
On Thu, 8 Sep 2016, Fenghua Yu wrote:
> +extern struct static_key rdt_enable_key;
> +void __intel_rdt_sched_in(void *dummy);
> +
> struct clos_cbm_table {
> unsigned long cbm;
> unsigned int clos_refcnt;
> };
>
> +/*
> + * intel_rdt_sched_in() - Writes the task's CLOSid to IA32_PQR_
From: Vikas Shivappa
Adds support for IA32_PQR_ASSOC MSR writes during task scheduling. For
Cache Allocation, MSR write would let the task fill in the cache
'subset' represented by the task's capacity bit mask.
The high 32 bits in the per processor MSR IA32_PQR_ASSOC represents the
CLOSid. Durin
5 matches
Mail list logo
