On 31.05.2018 11:37, Stefan Agner wrote:
> On 27.05.2018 23:54, Stefan Agner wrote:
>> Add support for the NAND flash controller found on NVIDIA
>> Tegra 2 SoCs. This implementation does not make use of the
>> command queue feature. Regular operations/data transfers are
>> done in PIO mode. Page re
On 27.05.2018 23:54, Stefan Agner wrote:
> Add support for the NAND flash controller found on NVIDIA
> Tegra 2 SoCs. This implementation does not make use of the
> command queue feature. Regular operations/data transfers are
> done in PIO mode. Page read/writes with hardware ECC make
> use of the D
On Mon, 28 May 2018 18:41:26 +0200
Benjamin Lindqvist wrote:
> Note that it's certainly possible to encode U-Boot and kernel with
> RS[4] and still use RS[8] for the rootfs even if the boot rom doesn't
> support it.
Not if you want to read/write from/to the uboot partition from Linux.
Per-parti
Note that it's certainly possible to encode U-Boot and kernel with
RS[4] and still use RS[8] for the rootfs even if the boot rom doesn't
support it. This whole 'use-bootable-ecc-only' business seems a bit
overengineered.
2018-05-28 14:43 GMT+02:00 Stefan Agner :
> On 28.05.2018 13:57, Dmitry Osipe
On 28.05.2018 13:57, Dmitry Osipenko wrote:
> On 28.05.2018 00:54, Stefan Agner wrote:
>> Add support for the NAND flash controller found on NVIDIA
>> Tegra 2 SoCs. This implementation does not make use of the
>> command queue feature. Regular operations/data transfers are
>> done in PIO mode. Page
On 28.05.2018 00:19, Miquel Raynal wrote:
> Hi Stefan,
>
> A few more comments here.
>
> On Sun, 27 May 2018 23:54:39 +0200, Stefan Agner
> wrote:
>
>> Add support for the NAND flash controller found on NVIDIA
>> Tegra 2 SoCs. This implementation does not make use of the
>> command queue featur
On 28.05.2018 00:54, Stefan Agner wrote:
> Add support for the NAND flash controller found on NVIDIA
> Tegra 2 SoCs. This implementation does not make use of the
> command queue feature. Regular operations/data transfers are
> done in PIO mode. Page read/writes with hardware ECC make
> use of the D
Hi Stefan,
A few more comments here.
On Sun, 27 May 2018 23:54:39 +0200, Stefan Agner
wrote:
> Add support for the NAND flash controller found on NVIDIA
> Tegra 2 SoCs. This implementation does not make use of the
> command queue feature. Regular operations/data transfers are
> done in PIO mode
Add support for the NAND flash controller found on NVIDIA
Tegra 2 SoCs. This implementation does not make use of the
command queue feature. Regular operations/data transfers are
done in PIO mode. Page read/writes with hardware ECC make
use of the DMA for data transfer.
Signed-off-by: Lucas Stach
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