On 06/03/2019 22:04, Martin Blumenstingl wrote:
> Hi Neil,
>
> On Mon, Mar 4, 2019 at 11:40 AM Neil Armstrong
> wrote:
> [...]
>> +static int phy_g12a_usb3_init(struct phy *phy)
>> +{
>> + struct phy_g12a_usb3_pcie_priv *priv = phy_get_drvdata(phy);
>> + int data, ret;
>> +
>> +
Hi Neil,
On Mon, Mar 4, 2019 at 11:40 AM Neil Armstrong wrote:
[...]
> +static int phy_g12a_usb3_init(struct phy *phy)
> +{
> + struct phy_g12a_usb3_pcie_priv *priv = phy_get_drvdata(phy);
> + int data, ret;
> +
> + /* Switch PHY to USB3 */
> + regmap_update_bits(priv->reg
This adds support for the shared USB3 + PCIE PHY found in the
Amlogic G12A SoC Family.
It supports USB3 Host mode or PCIE 2.0 mode, depending on the layout of
the board.
Selection is done by the #phy-cells, making the mode static and exclusive.
Signed-off-by: Neil Armstrong
---
drivers/phy/aml
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