On Tue, 19 Jun 2018 11:07:41 +0200
Miquel Raynal wrote:
> On Mon, 18 Jun 2018 22:41:03 +0200, Martin Kaiser
> wrote:
>
> > The v21 version of the NAND flash controller contains a Spare Area Size
> > Register (SPAS) at offset 0x10. Its setting defaults to the maximum
> > spare area size of 218 b
On Mon, 18 Jun 2018 22:41:03 +0200, Martin Kaiser
wrote:
> The v21 version of the NAND flash controller contains a Spare Area Size
> Register (SPAS) at offset 0x10. Its setting defaults to the maximum
> spare area size of 218 bytes. The size that is set in this register is
> used by the controlle
On Mon, 18 Jun 2018 22:41:03 +0200
Martin Kaiser wrote:
> The v21 version of the NAND flash controller contains a Spare Area Size
> Register (SPAS) at offset 0x10. Its setting defaults to the maximum
> spare area size of 218 bytes. The size that is set in this register is
> used by the controller
The v21 version of the NAND flash controller contains a Spare Area Size
Register (SPAS) at offset 0x10. Its setting defaults to the maximum
spare area size of 218 bytes. The size that is set in this register is
used by the controller when it calculates the ECC bytes internally in
hardware.
Usually
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