Hi Sascha,
Thanks for your comments.
On 05/19/2014 03:11 PM, Sascha Hauer wrote:
> On Fri, May 16, 2014 at 01:11:08PM +0800, Liu Ying wrote:
>> The i.MX PWM version2 is embedded in several i.MX SoCs,
>> such as i.MX27, i.MX51 and i.MX6SL. There are four 16bit
>> sample FIFOs in this IP, each of
On Fri, May 16, 2014 at 01:11:08PM +0800, Liu Ying wrote:
> The i.MX PWM version2 is embedded in several i.MX SoCs,
> such as i.MX27, i.MX51 and i.MX6SL. There are four 16bit
> sample FIFOs in this IP, each of which determines the duty
> period of a PWM waveform in one full cycle. The IP spec
> m
Hi Lothar,
Thanks for your review.
On 05/19/2014 01:53 PM, Lothar Waßmann wrote:
> Hi,
>
> Liu Ying wrote:
> [...]
>> @@ -30,6 +32,7 @@
>> /* i.MX27, i.MX31, i.MX35 share the same PWM function block: */
>>
>> #define MX3_PWMCR 0x00/* PWM Control Register */
>> +#define MX
Hi,
Liu Ying wrote:
[...]
> @@ -30,6 +32,7 @@
> /* i.MX27, i.MX31, i.MX35 share the same PWM function block: */
>
> #define MX3_PWMCR 0x00/* PWM Control Register */
> +#define MX3_PWMIR 0x08/* PWM Interrupt Register */
> #define MX3_PWMSAR
The i.MX PWM version2 is embedded in several i.MX SoCs,
such as i.MX27, i.MX51 and i.MX6SL. There are four 16bit
sample FIFOs in this IP, each of which determines the duty
period of a PWM waveform in one full cycle. The IP spec
mentions that we should not write a fourth sample because
the FIFOs w
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