Hi Brian,
On Mon, Feb 23, 2015 at 07:45:48PM -0800, Brian Norris wrote:
> On Tue, Feb 17, 2015 at 02:16:43PM -0300, Ezequiel Garcia wrote:
> > On 02/17/2015 02:07 PM, Robert Jarzmik wrote:
> > > It will be Brian choice eventually, but if you say that you will submit
> > > that
> > > approach for
On Tue, Feb 17, 2015 at 02:16:43PM -0300, Ezequiel Garcia wrote:
> On 02/17/2015 02:07 PM, Robert Jarzmik wrote:
> > It will be Brian choice eventually, but if you say that you will submit that
> > approach for next cycle, and yours for stable, and that for next you'll
> > convert
> > mdelay() to
On 02/17/2015 02:07 PM, Robert Jarzmik wrote:
> Maxime Ripard writes:
>
>> On Mon, Feb 16, 2015 at 10:36:02PM +0100, Robert Jarzmik wrote:
>>> diff --git a/drivers/mtd/nand/pxa3xx_nand.c b/drivers/mtd/nand/pxa3xx_nand.c
>>> index e512902..6e569e9 100644
>>> --- a/drivers/mtd/nand/pxa3xx_nand.c
>>
Maxime Ripard writes:
> On Mon, Feb 16, 2015 at 10:36:02PM +0100, Robert Jarzmik wrote:
>> diff --git a/drivers/mtd/nand/pxa3xx_nand.c b/drivers/mtd/nand/pxa3xx_nand.c
>> index e512902..6e569e9 100644
>> --- a/drivers/mtd/nand/pxa3xx_nand.c
>> +++ b/drivers/mtd/nand/pxa3xx_nand.c
>> @@ -576,11 +5
On Mon, Feb 16, 2015 at 10:36:02PM +0100, Robert Jarzmik wrote:
> diff --git a/drivers/mtd/nand/pxa3xx_nand.c b/drivers/mtd/nand/pxa3xx_nand.c
> index e512902..6e569e9 100644
> --- a/drivers/mtd/nand/pxa3xx_nand.c
> +++ b/drivers/mtd/nand/pxa3xx_nand.c
> @@ -576,11 +576,20 @@ static void start_data
On Mon, Feb 16, 2015 at 01:57:12PM -0300, Ezequiel Garcia wrote:
> On 02/16/2015 01:41 PM, Maxime Ripard wrote:
> > On Mon, Feb 16, 2015 at 05:27:53PM +0100, Thomas Petazzoni wrote:
> >> Dear Maxime Ripard,
> >>
> >> On Mon, 16 Feb 2015 13:51:11 +0100, Maxime Ripard wrote:
> >>
> >>> + whil
On Mon, Feb 16, 2015 at 10:36:02PM +0100, Robert Jarzmik wrote:
> Maxime Ripard writes:
>
> >> I don't think an mdelay(256) is acceptable.
> >
> > That's very true that this driver would need some love, but
> > valentine's day was last week.
>
> That doesn't cope with the 256ms mdelay. And a pote
Maxime Ripard writes:
>> I don't think an mdelay(256) is acceptable.
>
> That's very true that this driver would need some love, but
> valentine's day was last week.
That doesn't cope with the 256ms mdelay. And a potential big mdelay is not what
I'd call a bug fix, see below.
> I'm sorry, but th
Hi Robert,
On Mon, Feb 16, 2015 at 09:11:24PM +0100, Robert Jarzmik wrote:
> Maxime Ripard writes:
>
> > drivers/mtd/nand/pxa3xx_nand.c | 47
> > --
> > 1 file changed, 41 insertions(+), 6 deletions(-)
> >
> > diff --git a/drivers/mtd/nand/pxa3xx_nand.c
Maxime Ripard writes:
> drivers/mtd/nand/pxa3xx_nand.c | 47
> --
> 1 file changed, 41 insertions(+), 6 deletions(-)
>
> diff --git a/drivers/mtd/nand/pxa3xx_nand.c b/drivers/mtd/nand/pxa3xx_nand.c
> index 96b0b1d27df1..b2d8d6960765 100644
> --- a/drivers
-BEGIN PGP SIGNED MESSAGE-
Hash: SHA256
On 02/16/2015 01:41 PM, Maxime Ripard wrote:
> On Mon, Feb 16, 2015 at 05:27:53PM +0100, Thomas Petazzoni wrote:
>> Dear Maxime Ripard,
>>
>> On Mon, 16 Feb 2015 13:51:11 +0100, Maxime Ripard wrote:
>>
>>> + while (index < (len * 4)) {
>>>
On Mon, Feb 16, 2015 at 10:35:50AM -0300, Ezequiel Garcia wrote:
> On 02/16/2015 09:51 AM, Maxime Ripard wrote:
> > The NDDB register holds the data that are needed by the read and write
> > commands.
> >
> > However, during a read PIO access, the datasheet specifies that after each
> > 32
> > bi
On Mon, Feb 16, 2015 at 05:27:53PM +0100, Thomas Petazzoni wrote:
> Dear Maxime Ripard,
>
> On Mon, 16 Feb 2015 13:51:11 +0100, Maxime Ripard wrote:
>
> > + while (index < (len * 4)) {
> > + u32 timeout;
> > +
> > + __raw_readsl(info->mmio_base + NDDB
Dear Maxime Ripard,
On Mon, 16 Feb 2015 13:51:11 +0100, Maxime Ripard wrote:
> + while (index < (len * 4)) {
> + u32 timeout;
> +
> + __raw_readsl(info->mmio_base + NDDB, data + index, 8);
Are you guaranteed that 'len' is a multiple of 32 bytes
On 02/16/2015 09:51 AM, Maxime Ripard wrote:
> The NDDB register holds the data that are needed by the read and write
> commands.
>
> However, during a read PIO access, the datasheet specifies that after each 32
> bits read in that register, when BCH is enabled, we have to make sure that the
> RDD
Hi Maxime,
On Mon, 16 Feb 2015 13:51:11 +0100
Maxime Ripard wrote:
> The NDDB register holds the data that are needed by the read and write
> commands.
>
> However, during a read PIO access, the datasheet specifies that after each 32
> bits read in that register, when BCH is enabled, we have to
The NDDB register holds the data that are needed by the read and write
commands.
However, during a read PIO access, the datasheet specifies that after each 32
bits read in that register, when BCH is enabled, we have to make sure that the
RDDREQ bit is set in the NDSR register.
This fixes an issue
17 matches
Mail list logo
