Hi Yogesh,
On 13.11.18 09:22, Yogesh Narayan Gaur wrote:
[...]
>> +
>> +static void fsl_qspi_read_ahb(struct fsl_qspi *q, const struct
>> +spi_mem_op *op) {
>> +/*
>> + * We want to avoid needing to invalidate the cache by issueing
>> + * a reset to the AHB and Serial Flash domain, as
Hi Yogesh,
On 13.11.18 09:22, Yogesh Narayan Gaur wrote:
[...]
>> +
>> +static void fsl_qspi_read_ahb(struct fsl_qspi *q, const struct
>> +spi_mem_op *op) {
>> +/*
>> + * We want to avoid needing to invalidate the cache by issueing
>> + * a reset to the AHB and Serial Flash domain, as
ayan Gaur
> > ; Han Xu ;
> > shawn...@kernel.org; Frieder Schrempf ;
> > linux- ker...@vger.kernel.org
> > Subject: [PATCH v4 01/10] spi: Add a driver for the Freescale/NXP
> > QuadSPI controller
> >
> > From: Frieder Schrempf
> >
> > This driver i
ayan Gaur
> > ; Han Xu ;
> > shawn...@kernel.org; Frieder Schrempf ;
> > linux- ker...@vger.kernel.org
> > Subject: [PATCH v4 01/10] spi: Add a driver for the Freescale/NXP
> > QuadSPI controller
> >
> > From: Frieder Schrempf
> >
> > This driver i
forpe...@gmail.com;
> marek.va...@gmail.com; rich...@nod.at; miquel.ray...@bootlin.com;
> broo...@kernel.org; David Wolfe ; Fabio Estevam
> ; Prabhakar Kushwaha
> ; Yogesh Narayan Gaur
> ; Han Xu ;
> shawn...@kernel.org; Frieder Schrempf ; linux-
> ker...@vger.kernel.org
> S
forpe...@gmail.com;
> marek.va...@gmail.com; rich...@nod.at; miquel.ray...@bootlin.com;
> broo...@kernel.org; David Wolfe ; Fabio Estevam
> ; Prabhakar Kushwaha
> ; Yogesh Narayan Gaur
> ; Han Xu ;
> shawn...@kernel.org; Frieder Schrempf ; linux-
> ker...@vger.kernel.org
> S
From: Frieder Schrempf
This driver is derived from the SPI NOR driver at
mtd/spi-nor/fsl-quadspi.c. It uses the new SPI memory interface
of the SPI framework to issue flash memory operations to up to
four connected flash chips (2 buses with 2 CS each).
The controller does not support generic
From: Frieder Schrempf
This driver is derived from the SPI NOR driver at
mtd/spi-nor/fsl-quadspi.c. It uses the new SPI memory interface
of the SPI framework to issue flash memory operations to up to
four connected flash chips (2 buses with 2 CS each).
The controller does not support generic
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