Re: [PATCH v4 1/2] mtd: nand: pxa3xx: Fix PIO FIFO draining

2015-03-02 Thread Gregory CLEMENT
On 28/02/2015 10:01, Brian Norris wrote: > On Wed, Feb 18, 2015 at 11:32:07AM +0100, Maxime Ripard wrote: >> The NDDB register holds the data that are needed by the read and write >> commands. >> >> However, during a read PIO access, the datasheet specifies that after each 32 >> bytes read in that

Re: [PATCH v4 1/2] mtd: nand: pxa3xx: Fix PIO FIFO draining

2015-02-28 Thread Brian Norris
On Wed, Feb 18, 2015 at 11:32:07AM +0100, Maxime Ripard wrote: > The NDDB register holds the data that are needed by the read and write > commands. > > However, during a read PIO access, the datasheet specifies that after each 32 > bytes read in that register, when BCH is enabled, we have to make

Re: [PATCH v4 1/2] mtd: nand: pxa3xx: Fix PIO FIFO draining

2015-02-18 Thread Ezequiel Garcia
-BEGIN PGP SIGNED MESSAGE- Hash: SHA256 On 02/18/2015 11:01 AM, Maxime Ripard wrote: > On Wed, Feb 18, 2015 at 10:40:02AM -0300, Ezequiel Garcia wrote: >> On 02/18/2015 07:32 AM, Maxime Ripard wrote: >>> The NDDB register holds the data that are needed by the read >>> and write commands. >

Re: [PATCH v4 1/2] mtd: nand: pxa3xx: Fix PIO FIFO draining

2015-02-18 Thread Maxime Ripard
On Wed, Feb 18, 2015 at 10:40:02AM -0300, Ezequiel Garcia wrote: > On 02/18/2015 07:32 AM, Maxime Ripard wrote: > > The NDDB register holds the data that are needed by the read and write > > commands. > > > > However, during a read PIO access, the datasheet specifies that after each > > 32 > > by

Re: [PATCH v4 1/2] mtd: nand: pxa3xx: Fix PIO FIFO draining

2015-02-18 Thread Ezequiel Garcia
On 02/18/2015 07:32 AM, Maxime Ripard wrote: > The NDDB register holds the data that are needed by the read and write > commands. > > However, during a read PIO access, the datasheet specifies that after each 32 > bytes read in that register, when BCH is enabled, we have to make sure that > the >

Re: [PATCH v4 1/2] mtd: nand: pxa3xx: Fix PIO FIFO draining

2015-02-18 Thread Boris Brezillon
On Wed, 18 Feb 2015 11:32:07 +0100 Maxime Ripard wrote: > The NDDB register holds the data that are needed by the read and write > commands. > > However, during a read PIO access, the datasheet specifies that after each 32 > bytes read in that register, when BCH is enabled, we have to make sure

[PATCH v4 1/2] mtd: nand: pxa3xx: Fix PIO FIFO draining

2015-02-18 Thread Maxime Ripard
The NDDB register holds the data that are needed by the read and write commands. However, during a read PIO access, the datasheet specifies that after each 32 bytes read in that register, when BCH is enabled, we have to make sure that the RDDREQ bit is set in the NDSR register. This fixes an issu