Re: [PATCH v4 2/3] dw_dmac: max_mem_width limits value for SRC/DST_TR_WID register

2012-09-03 Thread Andy Shevchenko
On Mon, Sep 3, 2012 at 4:06 PM, Hein Tibosch wrote: > 1. The first draft of the patches worked with the max allowable value for > the SRC_WIDTH & DST_WIDTH fields: 0,1,2,3... Viresh thought it was not > transparent enough, he suggested to make it simpler with a binary choice of > 32- or 64-bits, d

Re: [PATCH v4 2/3] dw_dmac: max_mem_width limits value for SRC/DST_TR_WID register

2012-09-03 Thread Hein Tibosch
On 9/3/2012 4:59 PM, Viresh Kumar wrote: > On 3 September 2012 14:19, Andy Shevchenko wrote: >> On Mon, Sep 3, 2012 at 11:30 AM, Viresh Kumar >> wrote: >>> Which register are you talking about? This configuration is outside of DMAC >>> controller and i am not sure if dw DMAC controller can do 12

Re: [PATCH v4 2/3] dw_dmac: max_mem_width limits value for SRC/DST_TR_WID register

2012-09-03 Thread Viresh Kumar
On 3 September 2012 14:19, Andy Shevchenko wrote: > On Mon, Sep 3, 2012 at 11:30 AM, Viresh Kumar wrote: >> Which register are you talking about? This configuration is outside of DMAC >> controller and i am not sure if dw DMAC controller can do 128 or 256 >> bit transfers. > SRC_WIDTH & DST_WIDTH

Re: [PATCH v4 2/3] dw_dmac: max_mem_width limits value for SRC/DST_TR_WID register

2012-09-03 Thread Andy Shevchenko
On Mon, Sep 3, 2012 at 11:30 AM, Viresh Kumar wrote: > On 3 September 2012 13:55, Andy Shevchenko wrote: >>> #define DW_MEM_WIDTH_64 0 /* default */ >>> #define DW_MEM_WIDTH_32 1 /* e.g. for avr32 */ >> There are 4 options: 32, 64, 128, and 256 bits. I would prefer to

Re: [PATCH v4 2/3] dw_dmac: max_mem_width limits value for SRC/DST_TR_WID register

2012-09-03 Thread Viresh Kumar
On 3 September 2012 13:55, Andy Shevchenko wrote: >> #define DW_MEM_WIDTH_64 0 /* default */ >> #define DW_MEM_WIDTH_32 1 /* e.g. for avr32 */ > There are 4 options: 32, 64, 128, and 256 bits. I would prefer to see > the value in conjunction with > real value in the reg

Re: [PATCH v4 2/3] dw_dmac: max_mem_width limits value for SRC/DST_TR_WID register

2012-09-03 Thread Andy Shevchenko
On Sun, Sep 2, 2012 at 8:54 PM, Hein Tibosch wrote: > From: Hein Tibosch > > v4: now based and tested on 3.6-rc4 > > The dw_dmac driver was earlier adapted to do 64-bit transfers on the memory > side (see https://lkml.org/lkml/2012/1/18/52) > This works on ARM platforms but for AVR32 (AP700x) the

[PATCH v4 2/3] dw_dmac: max_mem_width limits value for SRC/DST_TR_WID register

2012-09-02 Thread Hein Tibosch
From: Hein Tibosch v4: now based and tested on 3.6-rc4 The dw_dmac driver was earlier adapted to do 64-bit transfers on the memory side (see https://lkml.org/lkml/2012/1/18/52) This works on ARM platforms but for AVR32 (AP700x) the maximum allowed transfer size is 32-bits. This patch allows the