>
> This patch adds the memory bus node for Exynos4210 SoC. Exynos4210 SoC has
> one memory bus to translate data between DRAM and eMMC/sub-IPs because
> Exynos4210 must need only one regulator for memory bus.
>
> Following list specifies the detailed relation between memory bus clock and
> su
This patch adds the memory bus node for Exynos4210 SoC. Exynos4210 SoC has
one memory bus to translate data between DRAM and eMMC/sub-IPs because
Exynos4210 must need only one regulator for memory bus.
Following list specifies the detailed relation between memory bus clock and
sub-IPs:
- DMC/ACP c
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