Quoting Taniya Das (2018-10-04 05:01:27)
>
> On 9/29/2018 12:21 AM, Stephen Boyd wrote:
> > Quoting Taniya Das (2018-09-18 03:25:38)
> >> @@ -3469,6 +3495,8 @@ enum {
> >> [GCC_QSPI_CORE_CLK_SRC] = &gcc_qspi_core_clk_src.clkr,
> >> [GCC_QSPI_CORE_CLK] = &gcc_qspi_core_clk.clkr,
>
On 9/29/2018 12:21 AM, Stephen Boyd wrote:
Quoting Taniya Das (2018-09-18 03:25:38)
@@ -3469,6 +3495,8 @@ enum {
[GCC_QSPI_CORE_CLK_SRC] = &gcc_qspi_core_clk_src.clkr,
[GCC_QSPI_CORE_CLK] = &gcc_qspi_core_clk.clkr,
[GCC_QSPI_CNOC_PERIPH_AHB_CLK] = &gcc_qspi_cnoc_peri
Quoting Taniya Das (2018-09-18 03:25:38)
> @@ -3469,6 +3495,8 @@ enum {
> [GCC_QSPI_CORE_CLK_SRC] = &gcc_qspi_core_clk_src.clkr,
> [GCC_QSPI_CORE_CLK] = &gcc_qspi_core_clk.clkr,
> [GCC_QSPI_CNOC_PERIPH_AHB_CLK] = &gcc_qspi_cnoc_periph_ahb_clk.clkr,
> + [GCC_LPASS_Q6_AX
Add support for the lpass clock controller found on SDM845 based devices.
This would allow lpass peripheral loader drivers to control the clocks to
bring the subsystem out of reset.
LPASS clocks present on the global clock controller would be registered
with the clock framework based on the device
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