On 10/02/19 6:49 PM, Boris Brezillon wrote:
> On Tue, 5 Feb 2019 11:43:46 +0530
> Vignesh R wrote:
>
static int cqspi_setup_flash(struct cqspi_st *cqspi, struct device_node
*np)
{
- const struct spi_nor_hwcaps hwcaps = {
- .mask = SNOR_HWCAPS_READ |
On Tue, 5 Feb 2019 11:43:46 +0530
Vignesh R wrote:
> >> static int cqspi_setup_flash(struct cqspi_st *cqspi, struct device_node
> >> *np)
> >> {
> >> - const struct spi_nor_hwcaps hwcaps = {
> >> - .mask = SNOR_HWCAPS_READ |
> >> - SNOR_HWCAPS_READ_FAST |
> >> -
Hi,
On 29/01/19 9:02 PM, tudor.amba...@microchip.com wrote:
>
>
> On 01/28/2019 07:49 AM, Vignesh R wrote:
>> Cadence OSPI controller IP supports Octal IO (x8 IO lines),
>> It also has an integrated PHY. IP register layout is very
>> similar to existing QSPI IP except for additional bits to
On 01/28/2019 07:49 AM, Vignesh R wrote:
> Cadence OSPI controller IP supports Octal IO (x8 IO lines),
> It also has an integrated PHY. IP register layout is very
> similar to existing QSPI IP except for additional bits to support Octal
> and Octal DDR mode. Therefore, extend current driver to
Cadence OSPI controller IP supports Octal IO (x8 IO lines),
It also has an integrated PHY. IP register layout is very
similar to existing QSPI IP except for additional bits to support Octal
and Octal DDR mode. Therefore, extend current driver to support Octal
mode. Only Octal SDR read (1-1-8)mode
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