Re: [PATCH v5 3/8] clk: samsung: add BPLL rate table for Exynos 5422 SoC

Hi Chanwoo, On 3/6/19 2:31 AM, Chanwoo Choi wrote: > Hi Lukasz, > > I'm talking about it repeatedly. How many times already, I mentioned > that you have to resend the patch after completed the discussion. > > > I replied this v3 patch[2]. But, you didn't reply or answer anything > and then

Re: [PATCH v5 3/8] clk: samsung: add BPLL rate table for Exynos 5422 SoC

Hi Lukasz, I'm talking about it repeatedly. How many times already, I mentioned that you have to resend the patch after completed the discussion. I replied this v3 patch[2]. But, you didn't reply or answer anything and then just send the same patch without any consent. - Re: [PATCH v3 3/8]

[PATCH v5 3/8] clk: samsung: add BPLL rate table for Exynos 5422 SoC

Add new table rate for BPLL for Exynos5422 SoC supporting Dynamic Memory Controller frequencies for driver's DRAM timings. Signed-off-by: Lukasz Luba --- drivers/clk/samsung/clk-exynos5420.c | 13 - 1 file changed, 12 insertions(+), 1 deletion(-) diff --git