Vignesh, Franklin,
On Tue, 8 Mar 2016, Paul Walmsley wrote:
> On Mon, 7 Mar 2016, Franklin S Cooper Jr wrote:
>
> > From: Vignesh R
> >
> > Add hwmod entries for the PWMSS on DRA7.
> >
> > Set l4_root_clk_div as the main_clk of PWMSS. It is fixed-factored clock
> > equal to L4PER2_L3_GICLK/2(
On Mon, 7 Mar 2016, Franklin S Cooper Jr wrote:
> From: Vignesh R
>
> Add hwmod entries for the PWMSS on DRA7.
>
> Set l4_root_clk_div as the main_clk of PWMSS. It is fixed-factored clock
> equal to L4PER2_L3_GICLK/2(l3_iclk_div/2).
>
> Signed-off-by: Vignesh R
> [fcoo...@ti.com: Do not add e
From: Vignesh R
Add hwmod entries for the PWMSS on DRA7.
Set l4_root_clk_div as the main_clk of PWMSS. It is fixed-factored clock
equal to L4PER2_L3_GICLK/2(l3_iclk_div/2).
Signed-off-by: Vignesh R
[fcoo...@ti.com: Do not add eQEP, ePWM and eCAP hwmod entries]
Signed-off-by: Franklin S Cooper
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