Re: [PATCH v6 3/3] KVM: LAPIC: Apply change to TDCR right away to the timer

2017-10-06 21:59+0800, Wanpeng Li: > 2017-10-06 21:14 GMT+08:00 Radim Krčmář : > > 2017-10-05 18:54-0700, Wanpeng Li: > >> From: Wanpeng Li > >> > >> The description in the Intel SDM of how the divide configuration > >> register is used: "The APIC timer frequency will be the processor's bus > >> c

Re: [PATCH v6 3/3] KVM: LAPIC: Apply change to TDCR right away to the timer

2017-10-06 21:14 GMT+08:00 Radim Krčmář : > 2017-10-05 18:54-0700, Wanpeng Li: >> From: Wanpeng Li >> >> The description in the Intel SDM of how the divide configuration >> register is used: "The APIC timer frequency will be the processor's bus >> clock or core crystal clock frequency divided by t

Re: [PATCH v6 3/3] KVM: LAPIC: Apply change to TDCR right away to the timer

2017-10-05 18:54-0700, Wanpeng Li: > From: Wanpeng Li > > The description in the Intel SDM of how the divide configuration > register is used: "The APIC timer frequency will be the processor's bus > clock or core crystal clock frequency divided by the value specified in > the divide configuration

[PATCH v6 3/3] KVM: LAPIC: Apply change to TDCR right away to the timer

From: Wanpeng Li The description in the Intel SDM of how the divide configuration register is used: "The APIC timer frequency will be the processor's bus clock or core crystal clock frequency divided by the value specified in the divide configuration register." Observation of baremetal shown tha