subject:"\[PATCH v7 02\/14\] clk\: tegra\: Don't enable PLLE HW sequencer at init"

Re: [PATCH v7 02/14] clk: tegra: Don't enable PLLE HW sequencer at init

2021-02-08 Thread Stephen Boyd

Quoting JC Kuo (2021-01-19 23:34:02) > PLLE hardware power sequencer references PEX/SATA UPHY PLL hardware > power sequencers' output to enable/disable PLLE. PLLE hardware power > sequencer has to be enabled only after PEX/SATA UPHY PLL's sequencers > are enabled. > > Signed-off-by: JC Kuo >

[PATCH v7 02/14] clk: tegra: Don't enable PLLE HW sequencer at init

2021-01-19 Thread JC Kuo

PLLE hardware power sequencer references PEX/SATA UPHY PLL hardware power sequencers' output to enable/disable PLLE. PLLE hardware power sequencer has to be enabled only after PEX/SATA UPHY PLL's sequencers are enabled. Signed-off-by: JC Kuo Acked-by: Thierry Reding --- v7: no change v6: