On Tue, Feb 2, 2021 at 1:18 PM Leizhen (ThunderTown)
wrote:
> On 2021/2/2 16:44, Arnd Bergmann wrote:
> >
> > To have a more useful performance number, try mentioning the
> > most performance sensitive non-coherent DMA master on one
> > of the chips that has this cache controller, and a
On 2021/2/2 16:44, Arnd Bergmann wrote:
> On Tue, Feb 2, 2021 at 8:16 AM Zhen Lei wrote:
>> +
>> +/*
>> + * All read and write operations on L3 cache registers are protected by the
>> + * spinlock, except for l3cache_init(). Each time the L3 cache operation is
>> + * performed, all related
On Tue, Feb 2, 2021 at 8:16 AM Zhen Lei wrote:
> +
> +/*
> + * All read and write operations on L3 cache registers are protected by the
> + * spinlock, except for l3cache_init(). Each time the L3 cache operation is
> + * performed, all related information is filled into its registers.
>
Add support for the Hisilicon Kunpeng L3 cache controller as used with
Kunpeng506 and Kunpeng509 SoCs.
These Hisilicon SoCs support LPAE, so the physical addresses is wider than
32-bits, but the actual bit width does not exceed 36 bits. When the cache
operation is performed based on the address
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