On Fri, 4 Nov 2016, Andrejczuk, Grzegorz wrote:
> >>On Tue, 1 Nov 2016, Grzegorz Andrejczuk wrote:
> >>
> >> +/* Intel Xeon Phi x200 ring 3 MONITOR/MWAIT */
> >
> > Oh well. I asked you to make that whole PHI thing go away.
> >
> > This is a feature which has nothing to do with PHI. It just happ
>>On Tue, 1 Nov 2016, Grzegorz Andrejczuk wrote:
>>
>> +/* Intel Xeon Phi x200 ring 3 MONITOR/MWAIT */
>
>Oh well. I asked you to make that whole PHI thing go away.
>
>This is a feature which has nothing to do with PHI. It just happens to be
>implemented on PHI. The FEATURES_ENABLES MSR is not
On Tue, 1 Nov 2016, Grzegorz Andrejczuk wrote:
>
> +/* Intel Xeon Phi x200 ring 3 MONITOR/MWAIT */
Oh well. I asked you to make that whole PHI thing go away.
This is a feature which has nothing to do with PHI. It just happens to be
implemented on PHI. The FEATURES_ENABLES MSR is not at all PHI
On Tue, Nov 01, 2016 at 11:14:47AM +0100, Grzegorz Andrejczuk wrote:
> Intel Xeon Phi x200 (codenamed Knights Landing) allows to enable
> MONITOR and MWAIT instructions outside of ring 0.
>
> The feature is controlled by MSR MISC_FEATURE_ENABLES (0x140).
> Setting bit 1 of this register enables it
Intel Xeon Phi x200 (codenamed Knights Landing) allows to enable
MONITOR and MWAIT instructions outside of ring 0.
The feature is controlled by MSR MISC_FEATURE_ENABLES (0x140).
Setting bit 1 of this register enables it, so MONITOR and MWAIT
instructions do not cause invalid-opcode exceptions when
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