Re: [PATCH v8 9/9] perf/amd/iommu: Enable support for multiple IOMMUs

On Fri, Feb 24, 2017 at 12:43:19AM +0700, Suravee Suthikulpanit wrote: > >Also, who cares about the banks, why is this exposed? > > The bank and counter values are not exposed to the user-space. > The amd_iommu PMU only expose, csource, devid, domid, pasid, devid_mask, > domid_mask, and

Re: [PATCH v8 9/9] perf/amd/iommu: Enable support for multiple IOMMUs

On Fri, Feb 24, 2017 at 12:43:19AM +0700, Suravee Suthikulpanit wrote: > >Also, who cares about the banks, why is this exposed? > > The bank and counter values are not exposed to the user-space. > The amd_iommu PMU only expose, csource, devid, domid, pasid, devid_mask, > domid_mask, and

Re: [PATCH v8 9/9] perf/amd/iommu: Enable support for multiple IOMMUs

On 2/24/17 01:11, Peter Zijlstra wrote: However, I have looked into reworking to not use the extra_regs, and I see that the union in struct hw_perf_event currently contains various PMU-specific structures (hardware, software, tracepoint, intel_cqm, itrace, amd_power, and breakpoint). For

Re: [PATCH v8 9/9] perf/amd/iommu: Enable support for multiple IOMMUs

On 2/24/17 01:11, Peter Zijlstra wrote: However, I have looked into reworking to not use the extra_regs, and I see that the union in struct hw_perf_event currently contains various PMU-specific structures (hardware, software, tracepoint, intel_cqm, itrace, amd_power, and breakpoint). For

Re: [PATCH v8 9/9] perf/amd/iommu: Enable support for multiple IOMMUs

Peter, On 2/14/17 19:31, Peter Zijlstra wrote: On Tue, Feb 07, 2017 at 08:57:52AM +0700, Suravee Suthikulpanit wrote: But instead it looks like you get the counter form: #define _GET_CNTR(ev) ((u8)(ev->hw.extra_reg.reg)) Which is absolutely insane. So, the IOMMU counters are

Re: [PATCH v8 9/9] perf/amd/iommu: Enable support for multiple IOMMUs

Peter, On 2/14/17 19:31, Peter Zijlstra wrote: On Tue, Feb 07, 2017 at 08:57:52AM +0700, Suravee Suthikulpanit wrote: But instead it looks like you get the counter form: #define _GET_CNTR(ev) ((u8)(ev->hw.extra_reg.reg)) Which is absolutely insane. So, the IOMMU counters are

Re: [PATCH v8 9/9] perf/amd/iommu: Enable support for multiple IOMMUs

On Tue, Feb 07, 2017 at 08:57:52AM +0700, Suravee Suthikulpanit wrote: > >But instead it looks like you get the counter form: > > > > #define _GET_CNTR(ev) ((u8)(ev->hw.extra_reg.reg)) > > > >Which is absolutely insane. > > > > So, the IOMMU counters are grouped into bank, and there could

Re: [PATCH v8 9/9] perf/amd/iommu: Enable support for multiple IOMMUs

On Tue, Feb 07, 2017 at 08:57:52AM +0700, Suravee Suthikulpanit wrote: > >But instead it looks like you get the counter form: > > > > #define _GET_CNTR(ev) ((u8)(ev->hw.extra_reg.reg)) > > > >Which is absolutely insane. > > > > So, the IOMMU counters are grouped into bank, and there could

Re: [PATCH v8 9/9] perf/amd/iommu: Enable support for multiple IOMMUs

Boris, On 1/25/17 16:55, Borislav Petkov wrote: On Wed, Jan 25, 2017 at 10:46:53AM +0100, Peter Zijlstra wrote: Which is absolutely insane. Right, IMO, the simplest thing to do for your purposes is to embed a struct amd_iommu pointer into struct perf_amd_iommu at init time so that you don't

Re: [PATCH v8 9/9] perf/amd/iommu: Enable support for multiple IOMMUs

Boris, On 1/25/17 16:55, Borislav Petkov wrote: On Wed, Jan 25, 2017 at 10:46:53AM +0100, Peter Zijlstra wrote: Which is absolutely insane. Right, IMO, the simplest thing to do for your purposes is to embed a struct amd_iommu pointer into struct perf_amd_iommu at init time so that you don't

Re: [PATCH v8 9/9] perf/amd/iommu: Enable support for multiple IOMMUs

Peter, On 1/25/17 16:46, Peter Zijlstra wrote: On Mon, Jan 16, 2017 at 01:23:36AM -0600, Suravee Suthikulpanit wrote: + pi = container_of(event->pmu, struct perf_amd_iommu, pmu); + hwc->idx = pi->idx; + hwc->config = event->attr.config; +

Re: [PATCH v8 9/9] perf/amd/iommu: Enable support for multiple IOMMUs

Peter, On 1/25/17 16:46, Peter Zijlstra wrote: On Mon, Jan 16, 2017 at 01:23:36AM -0600, Suravee Suthikulpanit wrote: + pi = container_of(event->pmu, struct perf_amd_iommu, pmu); + hwc->idx = pi->idx; + hwc->config = event->attr.config; +

Re: [PATCH v8 9/9] perf/amd/iommu: Enable support for multiple IOMMUs

Boris, On 1/23/17 02:55, Borislav Petkov wrote: @@ -421,46 +427,46 @@ static __init void amd_iommu_pc_exit(void) }; static __init int -_init_perf_amd_iommu(struct perf_amd_iommu *perf_iommu, char *name) +init_one_perf_amd_iommu(struct perf_amd_iommu *perf_iommu, unsigned int idx) {

Re: [PATCH v8 9/9] perf/amd/iommu: Enable support for multiple IOMMUs

Boris, On 1/23/17 02:55, Borislav Petkov wrote: @@ -421,46 +427,46 @@ static __init void amd_iommu_pc_exit(void) }; static __init int -_init_perf_amd_iommu(struct perf_amd_iommu *perf_iommu, char *name) +init_one_perf_amd_iommu(struct perf_amd_iommu *perf_iommu, unsigned int idx) {

Re: [PATCH v8 9/9] perf/amd/iommu: Enable support for multiple IOMMUs

On Wed, Jan 25, 2017 at 10:46:53AM +0100, Peter Zijlstra wrote: > Which is absolutely insane. Right, IMO, the simplest thing to do for your purposes is to embed a struct amd_iommu pointer into struct perf_amd_iommu at init time so that you don't have to do all that crazy dance in the PMU

Re: [PATCH v8 9/9] perf/amd/iommu: Enable support for multiple IOMMUs

On Wed, Jan 25, 2017 at 10:46:53AM +0100, Peter Zijlstra wrote: > Which is absolutely insane. Right, IMO, the simplest thing to do for your purposes is to embed a struct amd_iommu pointer into struct perf_amd_iommu at init time so that you don't have to do all that crazy dance in the PMU

Re: [PATCH v8 9/9] perf/amd/iommu: Enable support for multiple IOMMUs

On Mon, Jan 16, 2017 at 01:23:36AM -0600, Suravee Suthikulpanit wrote: > + pi = container_of(event->pmu, struct perf_amd_iommu, pmu); > + hwc->idx = pi->idx; > + hwc->config = event->attr.config; > + hwc->extra_reg.config = event->attr.config1; > static

Re: [PATCH v8 9/9] perf/amd/iommu: Enable support for multiple IOMMUs

On Mon, Jan 16, 2017 at 01:23:36AM -0600, Suravee Suthikulpanit wrote: > + pi = container_of(event->pmu, struct perf_amd_iommu, pmu); > + hwc->idx = pi->idx; > + hwc->config = event->attr.config; > + hwc->extra_reg.config = event->attr.config1; > static

Re: [PATCH v8 9/9] perf/amd/iommu: Enable support for multiple IOMMUs

On Mon, Jan 16, 2017 at 01:23:36AM -0600, Suravee Suthikulpanit wrote: > From: Suravee Suthikulpanit > > Add multi-IOMMU support for perf by exposing an AMD IOMMU PMU > for each IOMMU found in the system via: > > /bus/event_source/devices/amd_iommu_x > > where

Re: [PATCH v8 9/9] perf/amd/iommu: Enable support for multiple IOMMUs

On Mon, Jan 16, 2017 at 01:23:36AM -0600, Suravee Suthikulpanit wrote: > From: Suravee Suthikulpanit > > Add multi-IOMMU support for perf by exposing an AMD IOMMU PMU > for each IOMMU found in the system via: > > /bus/event_source/devices/amd_iommu_x > > where x is the IOMMU index. This

[PATCH v8 9/9] perf/amd/iommu: Enable support for multiple IOMMUs

From: Suravee Suthikulpanit Add multi-IOMMU support for perf by exposing an AMD IOMMU PMU for each IOMMU found in the system via: /bus/event_source/devices/amd_iommu_x where x is the IOMMU index. This allows users to specify different events to be programed

[PATCH v8 9/9] perf/amd/iommu: Enable support for multiple IOMMUs

From: Suravee Suthikulpanit Add multi-IOMMU support for perf by exposing an AMD IOMMU PMU for each IOMMU found in the system via: /bus/event_source/devices/amd_iommu_x where x is the IOMMU index. This allows users to specify different events to be programed onto performance counters of each