On Thu, Jan 08, 2015 at 08:53:55PM -0600, ttha...@opensource.altera.com wrote:
> +static int altr_edac_device_probe(struct platform_device *pdev)
> +{
> + struct edac_device_ctl_info *dci;
> + struct altr_edac_device_dev *drvdata;
> + struct resource *r;
> + int res = 0;
> + str
On 02/06/2015 01:17 PM, Mark Rutland wrote:
On Fri, Jan 09, 2015 at 02:53:55AM +, ttha...@opensource.altera.com wrote:
From: Thor Thayer
Adding L2 Cache and On-Chip RAM EDAC support for the
Altera SoCs using the EDAC device model. The SDRAM
controller is using the Memory Controller mode
On Fri, Jan 09, 2015 at 02:53:55AM +, ttha...@opensource.altera.com wrote:
> From: Thor Thayer
>
> Adding L2 Cache and On-Chip RAM EDAC support for the
> Altera SoCs using the EDAC device model. The SDRAM
> controller is using the Memory Controller model.
>
> Each type of ECC is individuall
From: Thor Thayer
Adding L2 Cache and On-Chip RAM EDAC support for the
Altera SoCs using the EDAC device model. The SDRAM
controller is using the Memory Controller model.
Each type of ECC is individually configurable.
The SDRAM ECC is a separate Kconfig option because:
1) the SDRAM preparation
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