* Jiri Olsa wrote:
> On Mon, Jan 28, 2013 at 06:49:55PM +0100, Stephane Eranian wrote:
> > On Sun, Jan 27, 2013 at 6:33 PM, Jiri Olsa wrote:
> > > hi,
> > > I was looking at the offcore stuff and it looks like we might
> > > be missing some constraints for offcore response events on
> > >
* Jiri Olsa jo...@redhat.com wrote:
On Mon, Jan 28, 2013 at 06:49:55PM +0100, Stephane Eranian wrote:
On Sun, Jan 27, 2013 at 6:33 PM, Jiri Olsa jo...@redhat.com wrote:
hi,
I was looking at the offcore stuff and it looks like we might
be missing some constraints for offcore response
On Mon, Jan 28, 2013 at 06:49:55PM +0100, Stephane Eranian wrote:
> On Sun, Jan 27, 2013 at 6:33 PM, Jiri Olsa wrote:
> > hi,
> > I was looking at the offcore stuff and it looks like we might
> > be missing some constraints for offcore response events on
> > Sandy/IvyBridge.
> >
> > The table
On Mon, Jan 28, 2013 at 06:49:55PM +0100, Stephane Eranian wrote:
On Sun, Jan 27, 2013 at 6:33 PM, Jiri Olsa jo...@redhat.com wrote:
hi,
I was looking at the offcore stuff and it looks like we might
be missing some constraints for offcore response events on
Sandy/IvyBridge.
The table
On Sun, Jan 27, 2013 at 6:33 PM, Jiri Olsa wrote:
> hi,
> I was looking at the offcore stuff and it looks like we might
> be missing some constraints for offcore response events on
> Sandy/IvyBridge.
>
> The table 18.8.5 (Off-core Response Performance Monitoring)
> in Intel SDM states PMC0 for
On Sun, Jan 27, 2013 at 6:33 PM, Jiri Olsa jo...@redhat.com wrote:
hi,
I was looking at the offcore stuff and it looks like we might
be missing some constraints for offcore response events on
Sandy/IvyBridge.
The table 18.8.5 (Off-core Response Performance Monitoring)
in Intel SDM states
hi,
I was looking at the offcore stuff and it looks like we might
be missing some constraints for offcore response events on
Sandy/IvyBridge.
The table 18.8.5 (Off-core Response Performance Monitoring)
in Intel SDM states PMC0 for 0xb7 and PMC3 for 0xbb, but
there's no other explanation or
hi,
I was looking at the offcore stuff and it looks like we might
be missing some constraints for offcore response events on
Sandy/IvyBridge.
The table 18.8.5 (Off-core Response Performance Monitoring)
in Intel SDM states PMC0 for 0xb7 and PMC3 for 0xbb, but
there's no other explanation or
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