On Tue, Sep 29, 2015 at 12:50 PM, Peter Zijlstra wrote:
>
> The control dependency creates a LOAD->STORE order, that is, no STOREs
> can happen until we observe !p->on_cpu.
Fair enough.
> Right, but wmb isn't sufficient as it doesn't order the prev->state LOAD
> vs the prev->on_cpu = 0 STORE. If
On Tue, Sep 29, 2015 at 12:40:22PM -0400, Linus Torvalds wrote:
> On Tue, Sep 29, 2015 at 8:45 AM, Peter Zijlstra wrote:
> >
> > +*
> > +* Pairs with the control dependency and rmb in try_to_wake_up().
> > */
>
> So this comment makes me nervous. A control dependency does
On Tue, Sep 29, 2015 at 8:45 AM, Peter Zijlstra wrote:
>
> +*
> +* Pairs with the control dependency and rmb in try_to_wake_up().
> */
So this comment makes me nervous. A control dependency doesn't
actually do anything on powerpc and ARM (or alpha, or MIPS, or any
number
Reviving a discussion at least a year old, I just remembered we had an
issue here while doing those PREEMPT_ACTIVE patches.
---
So the problem this patch is trying to address is as follows:
CPU0CPU1
context_switch(A, B)
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