On Thu, 15 Jan, at 11:59:42AM, H. Peter Anvin wrote:
> On 01/15/2015 11:41 AM, Matt Fleming wrote:
> >>
> >>Tianocore makes assumptions about the kernel's GDT layout? Yuck.
> >
> >No, but 32-bit Tianocore does rely on the second GDT entry being a
> >32-bit CS.
> >
> >It has no knowledge of
On 01/15/2015 11:41 AM, Matt Fleming wrote:
Tianocore makes assumptions about the kernel's GDT layout? Yuck.
No, but 32-bit Tianocore does rely on the second GDT entry being a
32-bit CS.
It has no knowledge of Linux's GDT layout.
If it assumes that descriptor 16 is a 32-bit CS (and what
On Wed, 14 Jan, at 10:27:47AM, Andy Lutomirski wrote:
>
> How are you manually triggering an MCE? I've been playing with some
> MCE stuff recently, but the only reasonably reliable way I know of to
> trigger an MCE is using WHEA, and I don't have a box with WHEA, and I
> assume your ASUS T100
On 01/15/2015 11:41 AM, Matt Fleming wrote:
Tianocore makes assumptions about the kernel's GDT layout? Yuck.
No, but 32-bit Tianocore does rely on the second GDT entry being a
32-bit CS.
It has no knowledge of Linux's GDT layout.
If it assumes that descriptor 16 is a 32-bit CS (and what
On Wed, 14 Jan, at 10:27:47AM, Andy Lutomirski wrote:
How are you manually triggering an MCE? I've been playing with some
MCE stuff recently, but the only reasonably reliable way I know of to
trigger an MCE is using WHEA, and I don't have a box with WHEA, and I
assume your ASUS T100 doesn't
On Thu, 15 Jan, at 11:59:42AM, H. Peter Anvin wrote:
On 01/15/2015 11:41 AM, Matt Fleming wrote:
Tianocore makes assumptions about the kernel's GDT layout? Yuck.
No, but 32-bit Tianocore does rely on the second GDT entry being a
32-bit CS.
It has no knowledge of Linux's GDT layout.
On Wed, Jan 14, 2015 at 10:47 AM, Borislav Petkov wrote:
> On Wed, Jan 14, 2015 at 10:38:25AM -0800, Andy Lutomirski wrote:
>> That's not a real MCE, though -- it happens synchronously instead of
>
> MCE can be synchronous in a sense too, as a result of executing an insn,
> for example, i.e.,
On Wed, Jan 14, 2015 at 10:38:25AM -0800, Andy Lutomirski wrote:
> That's not a real MCE, though -- it happens synchronously instead of
MCE can be synchronous in a sense too, as a result of executing an insn,
for example, i.e., EIPV bit set.
> at MCE priority with all the associated messiness.
On Wed, Jan 14, 2015 at 10:35 AM, Borislav Petkov wrote:
> On Wed, Jan 14, 2015 at 10:27:47AM -0800, Andy Lutomirski wrote:
>> How are you manually triggering an MCE? I've been playing with some
>> MCE stuff recently, but the only reasonably reliable way I know of to
>> trigger an MCE is using
On Wed, Jan 14, 2015 at 10:27:47AM -0800, Andy Lutomirski wrote:
> How are you manually triggering an MCE? I've been playing with some
> MCE stuff recently, but the only reasonably reliable way I know of to
> trigger an MCE is using WHEA, and I don't have a box with WHEA, and I
> assume your ASUS
On Wed, Jan 14, 2015 at 8:51 AM, Matt Fleming wrote:
> On Wed, 31 Dec, at 06:37:39PM, Matt Fleming wrote:
>> On Wed, 17 Dec, at 08:54:56AM, Andy Lutomirski wrote:
>> > > As far as I know, the only way to have continuously functional interrupt
>> > > handling across a long mode transition is to
On Wed, 31 Dec, at 06:37:39PM, Matt Fleming wrote:
> On Wed, 17 Dec, at 08:54:56AM, Andy Lutomirski wrote:
> > > As far as I know, the only way to have continuously functional interrupt
> > > handling across a long mode transition is to install an interrupt vector
> > > table and hope that CPUs
On Wed, Jan 14, 2015 at 10:38:25AM -0800, Andy Lutomirski wrote:
That's not a real MCE, though -- it happens synchronously instead of
MCE can be synchronous in a sense too, as a result of executing an insn,
for example, i.e., EIPV bit set.
at MCE priority with all the associated messiness. Or
On Wed, Jan 14, 2015 at 10:47 AM, Borislav Petkov b...@alien8.de wrote:
On Wed, Jan 14, 2015 at 10:38:25AM -0800, Andy Lutomirski wrote:
That's not a real MCE, though -- it happens synchronously instead of
MCE can be synchronous in a sense too, as a result of executing an insn,
for example,
On Wed, 31 Dec, at 06:37:39PM, Matt Fleming wrote:
On Wed, 17 Dec, at 08:54:56AM, Andy Lutomirski wrote:
As far as I know, the only way to have continuously functional interrupt
handling across a long mode transition is to install an interrupt vector
table and hope that CPUs actually do
On Wed, Jan 14, 2015 at 8:51 AM, Matt Fleming m...@console-pimps.org wrote:
On Wed, 31 Dec, at 06:37:39PM, Matt Fleming wrote:
On Wed, 17 Dec, at 08:54:56AM, Andy Lutomirski wrote:
As far as I know, the only way to have continuously functional interrupt
handling across a long mode
On Wed, Jan 14, 2015 at 10:27:47AM -0800, Andy Lutomirski wrote:
How are you manually triggering an MCE? I've been playing with some
MCE stuff recently, but the only reasonably reliable way I know of to
trigger an MCE is using WHEA, and I don't have a box with WHEA, and I
assume your ASUS
On Wed, Jan 14, 2015 at 10:35 AM, Borislav Petkov b...@alien8.de wrote:
On Wed, Jan 14, 2015 at 10:27:47AM -0800, Andy Lutomirski wrote:
How are you manually triggering an MCE? I've been playing with some
MCE stuff recently, but the only reasonably reliable way I know of to
trigger an MCE is
On Wed, 17 Dec, at 08:54:56AM, Andy Lutomirski wrote:
> [trying again with .org spelled correctly. also cc: bpetkov]
>
> On Wed, Dec 17, 2014 at 8:51 AM, Andy Lutomirski wrote:
> > I figured I should send this email before I forget about this issue:
> >
> > If you run perf record across any EFI
On Wed, 17 Dec, at 08:54:56AM, Andy Lutomirski wrote:
[trying again with .org spelled correctly. also cc: bpetkov]
On Wed, Dec 17, 2014 at 8:51 AM, Andy Lutomirski l...@amacapital.net wrote:
I figured I should send this email before I forget about this issue:
If you run perf record
[trying again with .org spelled correctly. also cc: bpetkov]
On Wed, Dec 17, 2014 at 8:51 AM, Andy Lutomirski wrote:
> I figured I should send this email before I forget about this issue:
>
> If you run perf record across any EFI mixed mode call or otherwise
> receive an NMI or MCE, the machine
I figured I should send this email before I forget about this issue:
If you run perf record across any EFI mixed mode call or otherwise
receive an NMI or MCE, the machine triple-faults. The cause is
straightforward: there is no valid IDT when we have long mode disabled
for the duration of the
I figured I should send this email before I forget about this issue:
If you run perf record across any EFI mixed mode call or otherwise
receive an NMI or MCE, the machine triple-faults. The cause is
straightforward: there is no valid IDT when we have long mode disabled
for the duration of the
[trying again with .org spelled correctly. also cc: bpetkov]
On Wed, Dec 17, 2014 at 8:51 AM, Andy Lutomirski l...@amacapital.net wrote:
I figured I should send this email before I forget about this issue:
If you run perf record across any EFI mixed mode call or otherwise
receive an NMI or
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