On Sun, Jan 17, 2021 at 02:44:04PM +, Zhang, Rui wrote:
> > But it doesn't fix anything.. there's not anything broken, except on that
> > daft
> > SPR thing.
>
> Well, yes.
> Before SPR, this is just a potential issue. But things on SPR suggests
> that this potential issue may become a real
el@vger.kernel.org; x...@kernel.org;
> kan.li...@linux.intel.com; a...@linux.intel.com
> Subject: Re: [PATCH 2/3] perf/x86/rapl: Fix energy counter detection
> Importance: High
>
> On Sat, Jan 16, 2021 at 08:19:35AM +, Zhang, Rui wrote:
> >
> >
> > > -Ori
gt; alexander.shish...@linux.intel.com; jo...@redhat.com;
> > namhy...@kernel.org; linux-kernel@vger.kernel.org; x...@kernel.org;
> > kan.li...@linux.intel.com; a...@linux.intel.com
> > Subject: Re: [PATCH 2/3] perf/x86/rapl: Fix energy counter detection
> > Importance: High
el@vger.kernel.org; x...@kernel.org;
> kan.li...@linux.intel.com; a...@linux.intel.com
> Subject: Re: [PATCH 2/3] perf/x86/rapl: Fix energy counter detection
> Importance: High
>
> On Fri, Jan 15, 2021 at 05:22:07PM +0800, Zhang Rui wrote:
> > In the RAPL ENERGY_COUNTER MSR, only
On Fri, Jan 15, 2021 at 05:22:07PM +0800, Zhang Rui wrote:
> In the RAPL ENERGY_COUNTER MSR, only the lower 32bits represent the
> energy counter, and the higher 32bits are reserved.
>
> Add the MSR mask for these MSRs to fix a problem that the RAPL PMU events
> are added erroneously when higher 3
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