On 10/16/19, 2:52 AM, 'Christoph Hellwig' wrote:
>
> On Tue, Oct 15, 2019 at 08:47:32PM +0530, Pankaj Dubey wrote:
> > OK, but do we think the current driver has only code which is being used by
> > some user?
>
> That is at least the intent of how we do kernel development.
Agreed!
>
> > At leas
On Tue, Oct 15, 2019 at 08:47:32PM +0530, Pankaj Dubey wrote:
> OK, but do we think the current driver has only code which is being used by
> some user?
That is at least the intent of how we do kernel development.
> At least I can see current driver has some features which is not being used
> by
lorenzo.pieral...@arm.com; gustavo.pimen...@synopsys.com;
> jingooh...@gmail.com; vid...@nvidia.com; 'Anvesh Salveru'
>
> Subject: Re: [PATCH v3] PCI: dwc: Add support to add GEN3 related
equalization
> quirks
>
> On Tue, Oct 15, 2019 at 02:28:00PM +0530, Pankaj Dubey w
On Tue, Oct 15, 2019 at 02:28:00PM +0530, Pankaj Dubey wrote:
> Is this something mandatory?
>
> As we discussed during first patch-set here [1] with Andrew, we have need of
> this patch (along with some other stuffs, which will be sent soon), to clean
> up our internal driver and make it ready fo
synopsys.com; jingooh...@gmail.com; vid...@nvidia.com;
> Anvesh Salveru
> Subject: Re: [PATCH v3] PCI: dwc: Add support to add GEN3 related
equalization
> quirks
>
> On Tue, Oct 15, 2019 at 08:29:22AM +0530, Pankaj Dubey wrote:
> > From: Anvesh Salveru
> >
> >
On Tue, Oct 15, 2019 at 08:29:22AM +0530, Pankaj Dubey wrote:
> From: Anvesh Salveru
>
> In some platforms, PCIe PHY may have issues which will prevent linkup
> to happen in GEN3 or higher speed. In case equalization fails, link will
> fallback to GEN1.
>
> DesignWare controller gives flexibilit
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