Hi Mike,
On Sat, Jan 26, 2013 at 03:50:32, Mike Turquette wrote:
> Is MULT_ROUND_UP doing the right thing for you in the clk_divider code?
> What is the clock rate requested of the parent PLL? I just want to make
> sure that we're doing the right thing in the basic divider code.
Actually
Hi Mike,
On Sat, Jan 26, 2013 at 03:50:32, Mike Turquette wrote:
Is MULT_ROUND_UP doing the right thing for you in the clk_divider code?
What is the clock rate requested of the parent PLL? I just want to make
sure that we're doing the right thing in the basic divider code.
Actually
Quoting Mohammed, Afzal (2013-01-25 04:18:22)
> Hi Paul,
>
> On Fri, Jan 25, 2013 at 13:48:11, Paul Walmsley wrote:
> > On Wed, 23 Jan 2013, Afzal Mohammed wrote:
>
> > > Currently round rate function would return proper rate iff requested
> > > rate exactly matches the PLL lockable rate. This
Quoting Mohammed, Afzal (2013-01-25 04:18:22)
Hi Paul,
On Fri, Jan 25, 2013 at 13:48:11, Paul Walmsley wrote:
On Wed, 23 Jan 2013, Afzal Mohammed wrote:
Currently round rate function would return proper rate iff requested
rate exactly matches the PLL lockable rate. This causes
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