On Fri, Jul 17, 2015 at 04:52:56PM -0700, Stephane Eranian wrote:
> On Fri, Jul 17, 2015 at 4:31 PM, Andi Kleen wrote:
> > On Fri, Jul 17, 2015 at 03:00:18PM -0700, Stephane Eranian wrote:
> >> Andi,
> >>
> >> On Fri, Jul 17, 2015 at 2:19 PM, Andi Kleen wrote:
> >> >> But then, the SDM is mislead
On Fri, Jul 17, 2015 at 4:31 PM, Andi Kleen wrote:
> On Fri, Jul 17, 2015 at 03:00:18PM -0700, Stephane Eranian wrote:
>> Andi,
>>
>> On Fri, Jul 17, 2015 at 2:19 PM, Andi Kleen wrote:
>> >> But then, the SDM is misleading. It is not describing what's
>> >> implemented for SKL.
>> >
>> > Actually
On Fri, Jul 17, 2015 at 03:00:18PM -0700, Stephane Eranian wrote:
> Andi,
>
> On Fri, Jul 17, 2015 at 2:19 PM, Andi Kleen wrote:
> >> But then, the SDM is misleading. It is not describing what's
> >> implemented for SKL.
> >
> > Actually it has a list of valid values you can put into the various
On Fri, 17 Jul 2015, Andi Kleen wrote:
> On Fri, Jul 17, 2015 at 11:05:37PM +0200, Peter Zijlstra wrote:
> > On Fri, Jul 17, 2015 at 10:52:33PM +0200, Andi Kleen wrote:
> > >
> > > I don't think the code is the right place to document such registers.
> >
> > If the code deviates from the SDM, it
On Fri, 17 Jul 2015, Andi Kleen wrote:
> On Fri, Jul 17, 2015 at 10:11:28PM +0200, Thomas Gleixner wrote:
> > On Fri, 17 Jul 2015, Andi Kleen wrote:
> >
> > > > I believe this mask of 0x3fff17 is wrong and should instead be
> > > > 0x7f based on the description of the FRONTEND
> > > > MSR I se
Andi,
On Fri, Jul 17, 2015 at 2:19 PM, Andi Kleen wrote:
>> But then, the SDM is misleading. It is not describing what's
>> implemented for SKL.
>
> Actually it has a list of valid values you can put into the various fields.
> None of them have the bits set you're trying to set.
>
You are talking
> But then, the SDM is misleading. It is not describing what's
> implemented for SKL.
Actually it has a list of valid values you can put into the various fields.
None of them have the bits set you're trying to set.
-Andi
--
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On Fri, Jul 17, 2015 at 11:05:37PM +0200, Peter Zijlstra wrote:
> On Fri, Jul 17, 2015 at 10:52:33PM +0200, Andi Kleen wrote:
> >
> > I don't think the code is the right place to document such registers.
>
> If the code deviates from the SDM, it _is_ the right place to explain,
> seeing how its t
On Fri, Jul 17, 2015 at 10:52:33PM +0200, Andi Kleen wrote:
>
> I don't think the code is the right place to document such registers.
If the code deviates from the SDM, it _is_ the right place to explain,
seeing how its the only place.
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On Fri, Jul 17, 2015 at 1:33 PM, Andi Kleen wrote:
> On Fri, Jul 17, 2015 at 10:11:28PM +0200, Thomas Gleixner wrote:
>> On Fri, 17 Jul 2015, Andi Kleen wrote:
>>
>> > > I believe this mask of 0x3fff17 is wrong and should instead be
>> > > 0x7f based on the description of the FRONTEND
>> > > M
On Fri, Jul 17, 2015 at 01:41:04PM -0700, Stephane Eranian wrote:
> Andi,
>
> On Fri, Jul 17, 2015 at 1:09 PM, Andi Kleen wrote:
> >> I believe this mask of 0x3fff17 is wrong and should instead be
> >> 0x7f based on the description of the FRONTEND
> >> MSR I see in the SDM Table 18-54 (bit 0-
Andi,
On Fri, Jul 17, 2015 at 1:09 PM, Andi Kleen wrote:
>> I believe this mask of 0x3fff17 is wrong and should instead be
>> 0x7f based on the description of the FRONTEND
>> MSR I see in the SDM Table 18-54 (bit 0-22 are valid). Otherwise, some
>> valid latency values may be rejected.
>
> No
On Fri, Jul 17, 2015 at 10:11:28PM +0200, Thomas Gleixner wrote:
> On Fri, 17 Jul 2015, Andi Kleen wrote:
>
> > > I believe this mask of 0x3fff17 is wrong and should instead be
> > > 0x7f based on the description of the FRONTEND
> > > MSR I see in the SDM Table 18-54 (bit 0-22 are valid). Othe
On Fri, 17 Jul 2015, Andi Kleen wrote:
> > I believe this mask of 0x3fff17 is wrong and should instead be
> > 0x7f based on the description of the FRONTEND
> > MSR I see in the SDM Table 18-54 (bit 0-22 are valid). Otherwise, some
> > valid latency values may be rejected.
>
> No, my mask is c
> I believe this mask of 0x3fff17 is wrong and should instead be
> 0x7f based on the description of the FRONTEND
> MSR I see in the SDM Table 18-54 (bit 0-22 are valid). Otherwise, some
> valid latency values may be rejected.
No, my mask is correct.
-Andi
--
a...@linux.intel.com -- Speaking
On Mon, Jun 29, 2015 at 2:22 PM, Andi Kleen wrote:
> From: Andi Kleen
>
> Skylake has a new FRONTEND_LATENCY PEBS event to accurate profile
> frontend problems (like ITLB or decoding issues)
>
> The new event is configured through a separate MSR, which selects
> a range of sub events.
>
> Define
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