On Fri, Jan 15, 2021 at 12:17:01PM -0300, Arnaldo Carvalho de Melo wrote:
[...]
> > > Thanks for the review, Jiri.
> > >
> > > Note, after testing with Arm SPE, we found the store operations don't
> > > contain the information for L1 cache hit or miss, this leads to there
> > > have no statistic
Em Mon, Jan 04, 2021 at 10:35:40AM +0100, Jiri Olsa escreveu:
> On Mon, Jan 04, 2021 at 10:09:38AM +0800, Leo Yan wrote:
>
> SNIP
>
> > > > Leo Yan (11):
> > > > perf c2c: Add dimensions for total load hit
> > > > perf c2c: Add dimensions for load hit
> > > > perf c2c: Add dimensions for lo
On Mon, Jan 04, 2021 at 10:09:38AM +0800, Leo Yan wrote:
SNIP
> > > Leo Yan (11):
> > > perf c2c: Add dimensions for total load hit
> > > perf c2c: Add dimensions for load hit
> > > perf c2c: Add dimensions for load miss
> > > perf c2c: Rename for shared cache line stats
> > > perf c2c:
On Sun, Jan 03, 2021 at 11:52:19PM +0100, Jiri Olsa wrote:
> On Sun, Dec 13, 2020 at 01:38:39PM +, Leo Yan wrote:
> > This patch set is to sort cache line for all load operations which hit
> > any cache levels. For single cache line view, it shows the load
> > references for loads with cache h
On Sun, Dec 13, 2020 at 01:38:39PM +, Leo Yan wrote:
> This patch set is to sort cache line for all load operations which hit
> any cache levels. For single cache line view, it shows the load
> references for loads with cache hits and with cache misses respectively.
>
> This series is a follo
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