On Tue, 2019-05-07 at 09:07 -0500, Bjorn Helgaas wrote:
> On Tue, May 07, 2019 at 02:02:34PM +0100, David Woodhouse wrote:
> > On Tue, 2019-05-07 at 07:49 -0500, Bjorn Helgaas wrote:
> > > No good reason; I just screwed up. Should be fixed in v5.2 (and marked
> > > for
> > > stable):
> > >
> > >
On Tue, May 07, 2019 at 02:02:34PM +0100, David Woodhouse wrote:
> On Tue, 2019-05-07 at 07:49 -0500, Bjorn Helgaas wrote:
> > No good reason; I just screwed up. Should be fixed in v5.2 (and marked for
> > stable):
> >
> > https://lore.kernel.org/linux-pci/20190318160718.10925-1-jean-philippe.bru
On Tue, 2019-05-07 at 07:49 -0500, Bjorn Helgaas wrote:
> No good reason; I just screwed up. Should be fixed in v5.2 (and marked for
> stable):
>
> https://lore.kernel.org/linux-pci/20190318160718.10925-1-jean-philippe.bruc...@arm.com
Aha, thanks. And I see 'dwc: Use devm_pci_alloc_host_bridge()
On Tue, May 07, 2019 at 01:00:03PM +0100, David Woodhouse wrote:
> On Fri, 2018-03-09 at 13:00 -0600, Bjorn Helgaas wrote:
> > --- a/drivers/pci/probe.c
> > +++ b/drivers/pci/probe.c
> > @@ -540,6 +540,16 @@ struct pci_host_bridge *pci_alloc_host_bridge(size_t
> > priv)
> > INIT_LIST_HEAD(
On Fri, 2018-03-09 at 13:00 -0600, Bjorn Helgaas wrote:
> --- a/drivers/pci/probe.c
> +++ b/drivers/pci/probe.c
> @@ -540,6 +540,16 @@ struct pci_host_bridge *pci_alloc_host_bridge(size_t
> priv)
> INIT_LIST_HEAD(&bridge->windows);
> bridge->dev.release = pci_release_host_bridge_de
On Mon, Mar 12, 2018 at 03:20:59PM +0100, Lukas Wunner wrote:
> On Mon, Mar 12, 2018 at 09:03:16AM -0500, Bjorn Helgaas wrote:
> > On Mon, Mar 12, 2018 at 01:04:02AM -0700, Christoph Hellwig wrote:
> > > > +* We assume we can manage these PCIe features. Some systems
> > > > may
> > > > +
On Mon, Mar 12, 2018 at 09:03:16AM -0500, Bjorn Helgaas wrote:
> On Mon, Mar 12, 2018 at 01:04:02AM -0700, Christoph Hellwig wrote:
> > > + * We assume we can manage these PCIe features. Some systems may
> > > + * reserve these for use by the platform itself, e.g., an ACPI BIOS
> > > + * may im
On Mon, Mar 12, 2018 at 01:04:02AM -0700, Christoph Hellwig wrote:
> > +* We assume we can manage these PCIe features. Some systems may
> > +* reserve these for use by the platform itself, e.g., an ACPI BIOS
> > +* may implement its own AER handling and use _OSC to prevent the
> > +
> + * We assume we can manage these PCIe features. Some systems may
> + * reserve these for use by the platform itself, e.g., an ACPI BIOS
> + * may implement its own AER handling and use _OSC to prevent the
> + * OS from interfering.
> + */
> + bridge->use_aer = 1;
>
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