Re: [PATCH v2 20/28] ARCv2: barriers

2015-06-23 Thread Will Deacon
On Tue, Jun 23, 2015 at 10:03:25AM +0100, Vineet Gupta wrote: > On Tuesday 23 June 2015 02:19 PM, Will Deacon wrote: > >> +/* > >> > + * MMIO can also get buffered/optimized in micro-arch, so barriers > >> > needed > >> > + * Based on ARM model for the typical use case > >> > + * > >> > + *

Re: [PATCH v2 20/28] ARCv2: barriers

2015-06-23 Thread Peter Zijlstra
On Tue, Jun 23, 2015 at 01:28:03PM +0530, Vineet Gupta wrote: > +/* > + * MMIO can also get buffered/optimized in micro-arch, so barriers needed > + * Based on ARM model for the typical use case > + * > + * > + * > + * or: > + * > + * > + * > + * http://www.spinics.net

Re: [PATCH v2 20/28] ARCv2: barriers

2015-06-23 Thread Vineet Gupta
Hi Will, On Tuesday 23 June 2015 02:19 PM, Will Deacon wrote: >> +/* >> > + * MMIO can also get buffered/optimized in micro-arch, so barriers needed >> > + * Based on ARM model for the typical use case >> > + * >> > + * >> > + * >> > + * or: >> > + * >> > + * > Th

Re: [PATCH v2 20/28] ARCv2: barriers

2015-06-23 Thread Will Deacon
Hi Vineet, On Tue, Jun 23, 2015 at 08:58:03AM +0100, Vineet Gupta wrote: > ARCv2 based HS38 cores are weakly ordered and thus explicit barriers for > kernel proper. > > SMP barrier is provided by DMB instruction which also guarantees local > barrier hence used as backend of smp_*mb() as well as *