Re: [PATCH v7 1/6] platform/x86: intel_pmc_ipc: fix gcr offset

2017-04-25 Thread sathyanarayanan kuppuswamy
On 04/25/2017 06:29 AM, Andy Shevchenko wrote: On Mon, Apr 10, 2017 at 1:00 AM, Kuppuswamy Sathyanarayanan wrote: According to Broxton APL spec, PMC MIMO resources for Global Control Registers(GCR) are located at 4K(0x1000) offset from IPC base

Re: [PATCH v7 1/6] platform/x86: intel_pmc_ipc: fix gcr offset

2017-04-25 Thread sathyanarayanan kuppuswamy
On 04/25/2017 06:29 AM, Andy Shevchenko wrote: On Mon, Apr 10, 2017 at 1:00 AM, Kuppuswamy Sathyanarayanan wrote: According to Broxton APL spec, PMC MIMO resources for Global Control Registers(GCR) are located at 4K(0x1000) offset from IPC base address. In this driver,

Re: [PATCH v7 1/6] platform/x86: intel_pmc_ipc: fix gcr offset

2017-04-25 Thread Andy Shevchenko
On Mon, Apr 10, 2017 at 1:00 AM, Kuppuswamy Sathyanarayanan wrote: > According to Broxton APL spec, PMC MIMO resources for Global Control > Registers(GCR) are located at 4K(0x1000) offset from IPC base address. > In this driver, PLAT_RESOURCE_GCR_OFFSET

Re: [PATCH v7 1/6] platform/x86: intel_pmc_ipc: fix gcr offset

2017-04-25 Thread Andy Shevchenko
On Mon, Apr 10, 2017 at 1:00 AM, Kuppuswamy Sathyanarayanan wrote: > According to Broxton APL spec, PMC MIMO resources for Global Control > Registers(GCR) are located at 4K(0x1000) offset from IPC base address. > In this driver, PLAT_RESOURCE_GCR_OFFSET macro defines the offset of GCR > region