On Monday, October 29, 2007 1:12 pm Keith Packard wrote:
> On Mon, 2007-10-29 at 12:47 -0700, Jesse Barnes wrote:
> > In this case, we're performing basically a
> > dma_sync*(...DMA_TO_DEVICE) right?
>
> But this is just for the GPU; every other DMA device in the system is
> cache-coherent.
Right.
On Monday, October 29, 2007 12:52 pm Dave Airlie wrote:
> > In this case, we're performing basically a
> > dma_sync*(...DMA_TO_DEVICE) right? Can we be sure that a single
> > flush is sufficient? Is there any window between when we flush and
> > when we start accessing memory with the device that
On Mon, 2007-10-29 at 12:47 -0700, Jesse Barnes wrote:
> In this case, we're performing basically a dma_sync*(...DMA_TO_DEVICE)
> right?
But this is just for the GPU; every other DMA device in the system is
cache-coherent.
> Can we be sure that a single flush is sufficient? Is there any
>
>
> In this case, we're performing basically a dma_sync*(...DMA_TO_DEVICE)
> right? Can we be sure that a single flush is sufficient? Is there any
> window between when we flush and when we start accessing memory with
> the device that we could get into more caching trouble?
Not that I can
On Monday, October 29, 2007 1:15 am Dave Airlie wrote:
> Hi,
>
> We've uncovered a need when using the new memory manager to flush the
> chipset global write buffers on certain intel chipset due to a lack
> of coherency..
>
> The attached patches add a new AGP interface for this purpose and
> impl
On Mon, 2007-10-29 at 08:15 +, Dave Airlie wrote:
> The attached patches add a new AGP interface for this purpose and
> implements this in the Intel AGP driver. This stuff is based of some
> guesswork in the 915 case from comments in the documentation :).
The relevant register lives in de
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