Hi Marc,
On 06/21/2016 02:41 PM, Marc Zyngier wrote:
>> Ok, so after discussing with some HW engineers, they said that even
>> if this is a pure router and cannot latch by itself, since the
>> devices themselves latch their IRQ output, reading the 4x32bit RAW
>> status registers could work as well
On 21/06/16 12:03, Sebastian Frias wrote:
> Hi Marc,
>
> On 06/21/2016 12:18 PM, Marc Zyngier wrote:
>>> Since irq-tango_v2.c is similar to irq-crossbar.c from TI (since it
>>> is based on it), I was wondering what is the policy or recommendation
>>> in such cases?
>>> Should I attempt to merge th
Hi Marc,
On 06/21/2016 12:18 PM, Marc Zyngier wrote:
>> Since irq-tango_v2.c is similar to irq-crossbar.c from TI (since it
>> is based on it), I was wondering what is the policy or recommendation
>> in such cases?
>> Should I attempt to merge the code (mainly the way to set up the
>> registers) o
[been away for a while, catching up...]
On 16/06/16 13:39, Sebastian Frias wrote:
> Hi Marc,
>
> On 06/14/2016 06:39 PM, Sebastian Frias wrote:
>> On 06/14/2016 06:37 PM, Sebastian Frias wrote:
>> Also, without seeing the code,
>> it is pretty difficult to make any meaningful comment...
>
Hi Marc,
On 06/14/2016 06:39 PM, Sebastian Frias wrote:
> On 06/14/2016 06:37 PM, Sebastian Frias wrote:
> Also, without seeing the code,
> it is pretty difficult to make any meaningful comment...
Base code is either 4.7rc1 or 4.4.
The irq-crossbar code is not much different
On 06/14/2016 06:37 PM, Sebastian Frias wrote:
Also, without seeing the code,
it is pretty difficult to make any meaningful comment...
>>>
>>> Base code is either 4.7rc1 or 4.4.
>>> The irq-crossbar code is not much different from TI, but you can find it
>>> attached.
>>
>> Please post i
Hi Marc,
On 06/13/2016 06:24 PM, Marc Zyngier wrote:
>> My understanding of "hierarchical irq domains" is that it is useful
>> when there are multiple stacked interrupt controllers. Also, the
>> documentation says "the majority of drivers should use the linear
>> map" (as opposed to the hierarchic
On Mon, Jun 13, 2016 at 05:46:19PM +0200, Sebastian Frias wrote:
> My understanding of "hierarchical irq domains" is that it is useful when
> there are multiple stacked interrupt controllers.
> Also, the documentation says "the majority of drivers should use the linear
> map" (as opposed to the h
On Mon, Jun 13, 2016 at 05:49:55PM +0200, Mason wrote:
> If I am not mistaken, the Cortex A9 MPCore GIC has 32 inputs.
>
> So any SoC with more than 32 devices capable of generating IRQs
> would have to share interrupts, right?
No, you simply add another interrupt controller to cascade it. That
On 13/06/16 16:15, Sebastian Frias wrote:
>>> The base file he was referring to is:
>>>
>>> https://git.kernel.org/cgit/linux/kernel/git/torvalds/linux.git/tree/arch/arm/boot/dts/tango4-common.dtsi
>>
>> I know which file that is, it is mentioned in the diff. I was merely
>> trying to point out th
Sebastian,
On 13/06/16 16:46, Sebastian Frias wrote:
> Hi Marc,
>
> Thanks for your reply, please find my comments below.
>
> On 06/10/2016 06:05 PM, Marc Zyngier wrote:
>> On 10/06/16 16:37, Sebastian Frias wrote:
>>> Hi,
>>>
>>> We are trying to write a driver for an interrupt controller (actu
On 13/06/16 16:49, Mason wrote:
> On 13/06/2016 17:42, Lennart Sorensen wrote:
>> On Mon, Jun 13, 2016 at 04:57:13PM +0200, Sebastian Frias wrote:
>>> Actually we have 128 inputs and 24 outputs, the 24 outputs go straight to
>>> the GIC.
>>> The HW block is a many-to-many router.
>>> There are 128
On 13/06/2016 17:42, Lennart Sorensen wrote:
> On Mon, Jun 13, 2016 at 04:57:13PM +0200, Sebastian Frias wrote:
>> Actually we have 128 inputs and 24 outputs, the 24 outputs go straight to
>> the GIC.
>> The HW block is a many-to-many router.
>> There are 128 32bit registers which specify, for eac
Hi Marc,
Thanks for your reply, please find my comments below.
On 06/10/2016 06:05 PM, Marc Zyngier wrote:
> On 10/06/16 16:37, Sebastian Frias wrote:
>> Hi,
>>
>> We are trying to write a driver for an interrupt controller (actually
>> more of a crossbar) for an ARM-based SoC. This IRQ crossbar
On Mon, Jun 13, 2016 at 04:57:13PM +0200, Sebastian Frias wrote:
> Actually we have 128 inputs and 24 outputs, the 24 outputs go straight to the
> GIC.
> The HW block is a many-to-many router.
> There are 128 32bit registers which specify, for each of the corresponding
> 128 inputs, to which of t
Hi Marc,
Thanks for your input, please find my comments below.
On 06/11/2016 11:58 AM, Marc Zyngier wrote:
>> I think Sebastian is even more baffled by the DT mess
>> (sorry, intricacies) than I am.
>
> This mess is what has saved us from the apocalypse 5 years ago, and
> describing a complex sy
Hi Lennart,
Thanks for your input, please find my comments below.
On 06/13/2016 04:04 PM, Lennart Sorensen wrote:
> On Sat, Jun 11, 2016 at 05:37:51PM +0200, Mason wrote:
>> Only the name of the file was provided, not the path. I was not aware
>> that you already knew where to find it. I made no
On Sat, Jun 11, 2016 at 05:37:51PM +0200, Mason wrote:
> Only the name of the file was provided, not the path. I was not aware
> that you already knew where to find it. I made no claim whatsoever on
> the implementation. In fact, I agree with everything Lennart wrote.
The way the TI irq crossbar w
On 12/06/16 14:50, Mason wrote:
> On 12/06/2016 12:00, Marc Zyngier wrote:
>
>> Mason wrote:
>>
>>> The problem with some Linux APIs is that they're logical and obvious
>>> to people who've been using them for years. For newcomers, it's not
>>> always so obvious.
>>>
>>> In this specific instance,
On 12/06/2016 12:00, Marc Zyngier wrote:
> Mason wrote:
>
>> The problem with some Linux APIs is that they're logical and obvious
>> to people who've been using them for years. For newcomers, it's not
>> always so obvious.
>>
>> In this specific instance, the problem statement seems rather simple
On Sat, 11 Jun 2016 17:37:51 +0200
Mason wrote:
> On 11/06/2016 11:58, Marc Zyngier wrote:
>
> > Mason wrote:
> >
> >> I think Sebastian is even more baffled by the DT mess
> >> (sorry, intricacies) than I am.
> >
> > This mess is what has saved us from the apocalypse 5 years ago, and
> > desc
On 11/06/2016 11:58, Marc Zyngier wrote:
> Mason wrote:
>
>> I think Sebastian is even more baffled by the DT mess
>> (sorry, intricacies) than I am.
>
> This mess is what has saved us from the apocalypse 5 years ago, and
> describing a complex system is not easy (what a surprise...).
The probl
On Fri, 10 Jun 2016 21:36:29 +0200
Mason wrote:
> On 10/06/2016 18:05, Marc Zyngier wrote:
>
> > On 10/06/16 16:37, Sebastian Frias wrote:
> >
> >> here's the diff on our DT:
> >>
> >> --- tango4-common.dtsi 2016-06-10 16:23:08.244246017 +0200
> >> +++ tangox_irqv2-common.dtsi 2016-06-
On 10/06/2016 18:05, Marc Zyngier wrote:
> On 10/06/16 16:37, Sebastian Frias wrote:
>
>> here's the diff on our DT:
>>
>> --- tango4-common.dtsi 2016-06-10 16:23:08.244246017 +0200
>> +++ tangox_irqv2-common.dtsi 2016-06-10 16:24:01.212588737 +0200
>> @@ -47,7 +47,7 @@
>>
>> soc {
>>
On Fri, Jun 10, 2016 at 05:37:30PM +0200, Sebastian Frias wrote:
> We are trying to write a driver for an interrupt controller (actually more of
> a crossbar) for an ARM-based SoC.
> This IRQ crossbar has 128 inputs and 24 outputs, the outputs are connected
> directly to the GIC.
> The idea is th
On 10/06/16 16:37, Sebastian Frias wrote:
> Hi,
>
> We are trying to write a driver for an interrupt controller (actually
> more of a crossbar) for an ARM-based SoC. This IRQ crossbar has 128
> inputs and 24 outputs, the outputs are connected directly to the
> GIC. The idea is that the GIC handles
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