On Fri, 16 Nov 2007, Oliver Neukum wrote:
> I am getting irq 19:nobody cared. Interrupts on 19 and 20 increase with
> same rate, disconnecting the device on the bus stops the increase,
> reconnecting it makes them increase again.
Very odd indeed. I suggest you post the relevant information (lik
Am Freitag 16 November 2007 schrieb Maciej W. Rozycki:
> On Fri, 16 Nov 2007, Oliver Neukum wrote:
>
> > > > On irq 20, there's an UHCI, on irq 19 is an EHCI. For every interrupt
> > > > on 20
> > > > there's a spurious interrupt on 19. USB devices on bus of the
> > > > controller on 20
> > > >
On Fri, 16 Nov 2007, Oliver Neukum wrote:
> > > On irq 20, there's an UHCI, on irq 19 is an EHCI. For every interrupt on
> > > 20
> > > there's a spurious interrupt on 19. USB devices on bus of the controller
> > > on 20
> > > work. So I know all interrupts are seen. ERR does not increase. Inter
Am Freitag 16 November 2007 schrieb Maciej W. Rozycki:
> On Thu, 15 Nov 2007, Oliver Neukum wrote:
>
> > On irq 20, there's an UHCI, on irq 19 is an EHCI. For every interrupt on 20
> > there's a spurious interrupt on 19. USB devices on bus of the controller on
> > 20
> > work. So I know all inter
On Thu, 15 Nov 2007, Oliver Neukum wrote:
> On irq 20, there's an UHCI, on irq 19 is an EHCI. For every interrupt on 20
> there's a spurious interrupt on 19. USB devices on bus of the controller on 20
> work. So I know all interrupts are seen. ERR does not increase. Interrupts
> for devices on the
Am Donnerstag 15 November 2007 schrieb Maciej W. Rozycki:
> On Thu, 15 Nov 2007, Oliver Neukum wrote:
> > I am seeing an interrupt for an UHCI on #20 CPU1 also arriving on
> > #19 CPU0, triggering the spurious interrupt detection.
>
> Well, if you see spurious interrupt detection triggered, then
On Thu, 15 Nov 2007, Oliver Neukum wrote:
> > Certainly. One possibility is to have multiple processors marked as the
> > destination, e.g. a logical delivery mode destination programmed with
> > multiple bits set.
>
> What would be the consequences?
It depends on the exact setup and condit
Am Donnerstag 15 November 2007 schrieb Maciej W. Rozycki:
> On Thu, 15 Nov 2007, Oliver Neukum wrote:
>
> > is there a way to so misprogramm an APIC that a physical interrupt results
> > in two interrupts delivered?
>
> Certainly. One possibility is to have multiple processors marked as the
>
On Thu, 15 Nov 2007, Oliver Neukum wrote:
> is there a way to so misprogramm an APIC that a physical interrupt results
> in two interrupts delivered?
Certainly. One possibility is to have multiple processors marked as the
destination, e.g. a logical delivery mode destination programmed with
m
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