Hi Miquel,
> "Miquel Raynal"
>
> Re: [PATCH 1/2] mtd: nand: ecc-bch: Fix the size of calc_buf/code_buf of
the BCH
>
> Hi YouChing,
>
> YouChing Lin wrote on Thu, 10 Dec 2020 11:22:08
> +0800:
>
(deleted)
> > The root cause is that the size of c
cate
> 64 bytes (cache size alignment).
>
> So we correct the size of calc_buf/code_buf to mtd->oobsize.
>
> Signed-off-by: YouChing Lin
> ---
> drivers/mtd/nand/ecc-sw-bch.c | 4 ++--
> 1 file changed, 2 insertions(+), 2 deletions(-)
>
> diff --git a/drivers/mtd/nand/
off-by: YouChing Lin
---
drivers/mtd/nand/ecc-sw-bch.c | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/drivers/mtd/nand/ecc-sw-bch.c b/drivers/mtd/nand/ecc-sw-bch.c
index 4d8a979..0a0ac11 100644
--- a/drivers/mtd/nand/ecc-sw-bch.c
+++ b/drivers/mtd/nand/ecc-sw-bch.c
@@ -237,8
On Fri, 17 May 2019 14:29:54 -0400, Kamal Dasu wrote:
> nand-ecc-strength and nand-ecc-step-size can be made optional as
> brcmanand driver can support using the nand_base driver detected
> values.
>
> Signed-off-by: Kamal Dasu
> ---
> Documentation/devicetree/bindings/mtd/
On Tue, 2019-05-21 at 14:44:21 UTC, Kamal Dasu wrote:
> nand-ecc-strength and nand-ecc-step-size can be made optional as
> brcmnand driver can support using raw NAND layer detected values.
>
> Signed-off-by: Kamal Dasu
Applied to https://git.kernel.org/pub/scm/linux/kernel/git/m
nand-ecc-strength and nand-ecc-step-size can be made optional as
brcmnand driver can support using raw NAND layer detected values.
Signed-off-by: Kamal Dasu
---
Documentation/devicetree/bindings/mtd/brcm,brcmnand.txt | 6 +++---
1 file changed, 3 insertions(+), 3 deletions(-)
diff --git a
Schrempf Frieder wrote on Tue, 21 May
2019 09:31:04 +:
> Hi Kamal,
>
> On 20.05.19 21:05, Kamal Dasu wrote:
> > nand-ecc-strength and nand-ecc-step-size can be made optional as
> > brcmnand driver can support using raw NAND layer detected values.
> >
&g
Hi Kamal,
On 20.05.19 21:05, Kamal Dasu wrote:
> nand-ecc-strength and nand-ecc-step-size can be made optional as
> brcmnand driver can support using raw NAND layer detected values.
>
> Signed-off-by: Kamal Dasu
> ---
> Documentation/devicetree/bindings/mtd/brcm,brcmnand.
Hi Kamal,
Kamal Dasu wrote on Mon, 20 May 2019 15:05:11
-0400:
> nand-ecc-strength and nand-ecc-step-size can be made optional as
> brcmnand driver can support using raw NAND layer detected values.
>
> Signed-off-by: Kamal Dasu
> ---
> Documentation/devicetree/bindings/mtd
nand-ecc-strength and nand-ecc-step-size can be made optional as
brcmnand driver can support using raw NAND layer detected values.
Signed-off-by: Kamal Dasu
---
Documentation/devicetree/bindings/mtd/brcm,brcmnand.txt | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a
Hi Kamal,
Kamal Dasu wrote on Fri, 17 May 2019 14:29:54
-0400:
> nand-ecc-strength and nand-ecc-step-size can be made optional as
> brcmanand driver can support using the nand_base driver detected
^ typo raw NAND layer
> values.
>
> Signed-off
nand-ecc-strength and nand-ecc-step-size can be made optional as
brcmanand driver can support using the nand_base driver detected
values.
Signed-off-by: Kamal Dasu
---
Documentation/devicetree/bindings/mtd/brcm,brcmnand.txt | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a
@@ -99,8 +99,6 @@
label = "pxa3xx_nand-0";
nand-rb = <0>;
nand-on-flash-bbt;
- nand-ecc-strength = <4>;
- nand-ecc-step-size = <512>;
partitions {
co
QCOM NAND controller supports only one step size (512) so
nand-ecc-step-size DT property is redundant. This property
can be removed and ecc step size can be assigned with 512 value.
Acked-by: Miquel Raynal
Signed-off-by: Abhishek Sahu
---
* Changes from v3:
1. Minor change in comment
(s
On 2018-05-26 14:12, Miquel Raynal wrote:
Hi Abhishek,
On Fri, 25 May 2018 17:51:33 +0530, Abhishek Sahu
wrote:
QCOM NAND controller supports only one step size (512) so
nand-ecc-step-size DT property is redundant. This property
can be removed and ecc step size can be assigned with 512 value
On 2018-05-26 14:12, Miquel Raynal wrote:
Hi Abhishek,
On Fri, 25 May 2018 17:51:31 +0530, Abhishek Sahu
wrote:
If nand-ecc-strength specified in DT, then controller will use
this ECC strength otherwise ECC strength will be calculated
according to chip requirement and available OOB size
Hi Abhishek,
On Fri, 25 May 2018 17:51:33 +0530, Abhishek Sahu
wrote:
> QCOM NAND controller supports only one step size (512) so
> nand-ecc-step-size DT property is redundant. This property
> can be removed and ecc step size can be assigned with 512 value.
>
> Signed-off-by
Hi Abhishek,
On Fri, 25 May 2018 17:51:31 +0530, Abhishek Sahu
wrote:
> If nand-ecc-strength specified in DT, then controller will use
> this ECC strength otherwise ECC strength will be calculated
> according to chip requirement and available OOB size.
>
> Signed-off-by
QCOM NAND controller supports only one step size (512) but
nand-ecc-step-size is required property in DT. This DT property
can be removed and ecc step size can be assigned in driver with
512 value.
Signed-off-by: Abhishek Sahu
---
Currently there is no user in mainline linux kernel for
QPIC
If nand-ecc-strength specified in DT, then controller will use
this ECC strength otherwise ECC strength will be calculated
according to chip requirement and available OOB size.
Signed-off-by: Abhishek Sahu
---
* Changes from v2:
NONE
* Changes from v1:
NEW PATCH
Documentation/devicetree
QCOM NAND controller supports only one step size (512) so
nand-ecc-step-size DT property is redundant. This property
can be removed and ecc step size can be assigned with 512 value.
Signed-off-by: Abhishek Sahu
---
* Changes from v2:
NEW CHANGE
1. Removed the custom logic and used the
On 2018-05-21 20:02, Miquel Raynal wrote:
Hi Abhishek,
On Thu, 3 May 2018 17:50:30 +0530, Abhishek Sahu
wrote:
Now, nand-ecc-strength is optional. If specified in DT, then
controller will use this ECC strength otherwise ECC strength will
be calculated according to chip requirement and
Hi Abhishek,
On Thu, 3 May 2018 17:50:30 +0530, Abhishek Sahu
wrote:
> Now, nand-ecc-strength is optional. If specified in DT, then
> controller will use this ECC strength otherwise ECC strength will
> be calculated according to chip requirement and available OOB size.
Same comment
On Thu, 3 May 2018 17:50:30 +0530
Abhishek Sahu wrote:
> Now, nand-ecc-strength is optional. If specified in DT, then
> controller will use this ECC strength otherwise ECC strength will
> be calculated according to chip requirement and available OOB size.
>
> Signed-off-by
Now, nand-ecc-strength is optional. If specified in DT, then
controller will use this ECC strength otherwise ECC strength will
be calculated according to chip requirement and available OOB size.
Signed-off-by: Abhishek Sahu
---
* Changes from v1:
NEW PATCH
Documentation/devicetree/bindings
On 28 April 2018 at 06:19, Vivek Unune wrote:
> On Fri, Apr 27, 2018 at 10:05 AM, Vivek Unune wrote:
>> On Wed, Apr 25, 2018 at 11:02:04AM +0200, Rafał Miłecki wrote:
>>>
>>> The easiest solution: ignore all these "error -74 (ECC error) while
>>> reading" errors (they may last for few minutes!).
On Fri, Apr 27, 2018 at 10:05 AM, Vivek Unune wrote:
> On Wed, Apr 25, 2018 at 11:02:04AM +0200, Rafał Miłecki wrote:
>>
>> The easiest solution: ignore all these "error -74 (ECC error) while
>> reading" errors (they may last for few minutes!). I believe UBI should
>> simply recreate all pages it
On Wed, Apr 25, 2018 at 11:02:04AM +0200, Rafał Miłecki wrote:
> > [ 13.530863] ubi0 warning: 0xc037c9e4: error -74 (ECC error) while
> > reading 64 bytes from PEB 115:0, read only 64 bytes, retry
> > [ 13.542763] ubi0 warning: 0xc037c9e4: error -74 (ECC error) while
> > reading 64 bytes from
On 13.03.2018 02:02, Vivek Unune wrote:
On Mon, Mar 12, 2018 at 03:52:27PM -0700, Florian Fainelli wrote:
On 03/11/2018 03:03 AM, Vivek Unune wrote:
Hi Rafał,
On Sat, Mar 10, 2018 at 10:41:04PM +0100, Rafał Miłecki wrote:
On 10 March 2018 at 18:12, Vivek Unune wrote:
Using BCH8 gives ecc er
On 11 March 2018 at 11:03, Vivek Unune wrote:
> Hi Rafał,
>
> On Sat, Mar 10, 2018 at 10:41:04PM +0100, Rafał Miłecki wrote:
>> On 10 March 2018 at 18:12, Vivek Unune wrote:
>> > Using BCH8 gives ecc errors and makes the router unsuable.
>> > Switching to BCH1 fixes these errors.
>>
>> Can you pr
Hi Florian,
On Mon, Mar 12, 2018 at 03:52:27PM -0700, Florian Fainelli wrote:
> On 03/11/2018 03:03 AM, Vivek Unune wrote:
> > Hi Rafał,
> >
> > On Sat, Mar 10, 2018 at 10:41:04PM +0100, Rafał Miłecki wrote:
> >> On 10 March 2018 at 18:12, Vivek Unune wrote:
> >>> Using BCH8 gives ecc errors and
On 03/11/2018 03:03 AM, Vivek Unune wrote:
> Hi Rafał,
>
> On Sat, Mar 10, 2018 at 10:41:04PM +0100, Rafał Miłecki wrote:
>> On 10 March 2018 at 18:12, Vivek Unune wrote:
>>> Using BCH8 gives ecc errors and makes the router unsuable.
>>> Switching to BCH1 fixes these errors.
>>
>> Can you provide
Hi Rafał,
On Sat, Mar 10, 2018 at 10:41:04PM +0100, Rafał Miłecki wrote:
> On 10 March 2018 at 18:12, Vivek Unune wrote:
> > Using BCH8 gives ecc errors and makes the router unsuable.
> > Switching to BCH1 fixes these errors.
>
> Can you provide CFE's log messages starting with
> "Decompressing.
On 10 March 2018 at 18:12, Vivek Unune wrote:
> Using BCH8 gives ecc errors and makes the router unsuable.
> Switching to BCH1 fixes these errors.
Can you provide CFE's log messages starting with
"Decompressing...done" and up to the "Press Ctrl+C to stop in CFE"
please? I'd like to see what NAND
Using BCH8 gives ecc errors and makes the router unsuable.
Switching to BCH1 fixes these errors.
Signed-off-by: Vivek Unune
---
arch/arm/boot/dts/bcm47094-linksys-panamera.dts | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/arch/arm/boot/dts/bcm47094-linksys-panamera.dts
b/a
dea, except I would do this slightly differently to avoid
>> >> > declaring all combinations of stepsize and strengths
>> >> >
>> >> > struct nand_ecc_stepsize_info {
>> >> > int stepsize;
>> >> > int ns
>> > };
> >> >
> >> > int nand_try_to_match_ecc_req(struct nand_chip *chip,
> >> > const struct nand_ecc_engine_caps *caps,
> >> > struct nand_ecc_spec *spec)
> >> > {
>
negative error code
>> > * otherwise.
>> > */
>> > }
>> >
>> > Note that nand_try_to_match_ecc_req() has to be more generic than
>> > denali_try_to_match_ecc_req() WRT step sizes, which will probably
>> > comple
_ecc_req() WRT step sizes, which will probably
> > complexify the logic.
>
>
> After I fiddle with this generic approach for a while,
> I started to feel like giving up.
I don't get it. What was the problem with my initial suggestion (the
denali specific one, not the g
Hi Boris,
2017-04-10 1:33 GMT+09:00 Boris Brezillon :
> On Mon, 3 Apr 2017 12:16:34 +0900
> Masahiro Yamada wrote:
>
>> Hi Boris,
>>
>>
>>
>> 2017-03-31 18:46 GMT+09:00 Boris Brezillon
>> :
>>
>> > You can try something like that when no explicit ecc.strength and
>> > ecc.size has been set in
On Mon, 3 Apr 2017 12:16:34 +0900
Masahiro Yamada wrote:
> Hi Boris,
>
>
>
> 2017-03-31 18:46 GMT+09:00 Boris Brezillon
> :
>
> > You can try something like that when no explicit ecc.strength and
> > ecc.size has been set in the DT and when ECC_MAXIMIZE was not passed.
> >
> > static int
> >
Hi Boris,
2017-03-31 18:46 GMT+09:00 Boris Brezillon :
> You can try something like that when no explicit ecc.strength and
> ecc.size has been set in the DT and when ECC_MAXIMIZE was not passed.
>
> static int
> denali_get_closest_ecc_strength(struct denali_nand_info *denali,
>
CC strength as
> >> possible, but it would be reasonable to allow DT to set a particular
> >> ECC strength with "nand-ecc-strength" property. This is useful
> >> when a particular ECC setting is hard-coded by firmware (or hard-
> >> wired by bo
Hi Boris,
2017-03-30 23:02 GMT+09:00 Boris Brezillon :
> On Thu, 30 Mar 2017 15:46:00 +0900
> Masahiro Yamada wrote:
>
>> Historically, this driver tried to choose as big ECC strength as
>> possible, but it would be reasonable to allow DT to set a particular
>>
On Thu, 30 Mar 2017 15:46:00 +0900
Masahiro Yamada wrote:
> Historically, this driver tried to choose as big ECC strength as
> possible, but it would be reasonable to allow DT to set a particular
> ECC strength with "nand-ecc-strength" property. This is useful
> when a par
Historically, this driver tried to choose as big ECC strength as
possible, but it would be reasonable to allow DT to set a particular
ECC strength with "nand-ecc-strength" property. This is useful
when a particular ECC setting is hard-coded by firmware (or hard-
wired by boot ROM).
On Sun, Nov 27, 2016 at 03:06:23AM +0900, Masahiro Yamada wrote:
> Historically, this driver tried to choose as big ECC strength as
> possible, but it would be reasonable to allow DT to set a particular
> ECC strength with "nand-ecc-strength" property.
>
> Going for
Historically, this driver tried to choose as big ECC strength as
possible, but it would be reasonable to allow DT to set a particular
ECC strength with "nand-ecc-strength" property.
Going forward, DT platforms should specify "nand-ecc-strength" or
"nand-ecc-maximize&
Le 06/06/2016 00:43, Rafał Miłecki a écrit :
> This device uses BCH-1 instead of BCH-8. This fixes ECC errors and makes
> NAND usable with brcmnand.
>
> Signed-off-by: Rafał Miłecki
And also applied, thanks!
--
Florian
e 100644
index 000..24b099c
--- /dev/null
+++ b/arch/arm/boot/dts/bcm5301x-nand-cs0-bch1.dtsi
@@ -0,0 +1,15 @@
+/*
+ * Broadcom Northstar NAND.
+ *
+ * Copyright (C) 2016 Rafał Miłecki
+ *
+ * Licensed under the ISC license.
+ */
+
+#include "bcm5301x-nand-cs0.dtsi"
+
+&nandcs {
+
On Fri, 22 Apr 2016 13:23:13 +0200
Rafał Miłecki wrote:
> So far it was only possible to specify ECC algorithm using "soft" and
> "soft_bch" values of nand-ecc-mode prop. There wasn't a way to specify
> it for a hardware ECC mode.
>
> Now that we have
On Fri, 22 Apr 2016 13:23:14 +0200
Rafał Miłecki wrote:
> Now that we support nand-ecc-algo property it should be used together
> with "soft" to specify software BCH ECC.
>
> Signed-off-by: Rafał Miłecki
> ---
> Documentation/devicetree/bindings/mtd/nand.txt | 6
On Fri, Apr 22, 2016 at 01:23:14PM +0200, Rafał Miłecki wrote:
> Now that we support nand-ecc-algo property it should be used together
> with "soft" to specify software BCH ECC.
>
> Signed-off-by: Rafał Miłecki
> ---
> Documentation/devicetree/bindings/mtd/nand.txt
On Fri, Apr 22, 2016 at 01:23:13PM +0200, Rafał Miłecki wrote:
> So far it was only possible to specify ECC algorithm using "soft" and
> "soft_bch" values of nand-ecc-mode prop. There wasn't a way to specify
> it for a hardware ECC mode.
>
> Now that we
On Fri, 22 Apr 2016 13:23:13 +0200
Rafał Miłecki wrote:
> So far it was only possible to specify ECC algorithm using "soft" and
> "soft_bch" values of nand-ecc-mode prop. There wasn't a way to specify
> it for a hardware ECC mode.
>
> Now that we have
Now that we support nand-ecc-algo property it should be used together
with "soft" to specify software BCH ECC.
Signed-off-by: Rafał Miłecki
---
Documentation/devicetree/bindings/mtd/nand.txt | 6 --
1 file changed, 4 insertions(+), 2 deletions(-)
diff --git a/Documentation/
So far it was only possible to specify ECC algorithm using "soft" and
"soft_bch" values of nand-ecc-mode prop. There wasn't a way to specify
it for a hardware ECC mode.
Now that we have independent field in NAND subsystem for storing info
about ECC algorithm we may also
Around Fri 15 Apr 2016 21:54:03 +0200 or thereabout, Rafał Miłecki wrote:
> This is part of process deprecating NAND_ECC_SOFT_BCH (and switching to
> enum nand_ecc_algo).
>
> Signed-off-by: Rafał Miłecki
Acked-by: Hans-Christian Noren Egtvedt
> ---
> arch/avr32/boards/atngw100/setup.c |
On Fri, 15 Apr 2016 21:54:03 +0200
Rafał Miłecki wrote:
> This is part of process deprecating NAND_ECC_SOFT_BCH (and switching to
> enum nand_ecc_algo).
Not sure we really need to add this ->ecc_algo field: none of the
existing AVR32 boards use software BCH implementation, and I don't
expect to
This is part of process deprecating NAND_ECC_SOFT_BCH (and switching to
enum nand_ecc_algo).
Signed-off-by: Rafał Miłecki
---
arch/avr32/boards/atngw100/setup.c | 1 +
arch/avr32/boards/atstk1000/atstk1002.c | 1 +
include/linux/platform_data/atmel.h | 1 +
3 files changed, 3 insertions
Hi,
I have the following confusions regarding the nand ecc algorithms:
Haming and BCH
Request your help to clarify the below concerns.
Hamming Mode:
What will happen if the data has more than two bit errors for codeword?
Will the nand_correct_data() function returns uncorrectable ecc
oto out_free_cs;
- gpmc_update_nand_reg(&gpmc_nand_data->reg, gpmc_nand_data->cs);
-
if (!gpmc_hwecc_bch_capable(gpmc_nand_data->ecc_opt)) {
dev_err(dev, "Unsupported NAND ECC scheme selected\n");
return -EINVAL;
diff --git a/arch/ar
rring).
> >
> > On Wed, Feb 05, 2014 at 02:34:44PM +0100, Boris BREZILLON wrote:
> >> On 05/02/2014 12:15, Grant Likely wrote:
> >> > On Wed, 29 Jan 2014 14:53:32 -0300, Ezequiel Garcia
> >> > wrote:
> > [..]
> >> >>
> >> &
> On 05/02/2014 12:15, Grant Likely wrote:
>> > On Wed, 29 Jan 2014 14:53:32 -0300, Ezequiel Garcia
>> > wrote:
> [..]
>> >>
>> >> Maybe we can discuss about it now?
>> >>
>> >>nand-ecc-strength : integer ECC required stren
Ezequiel Garcia
> > wrote:
[..]
> >>
> >> Maybe we can discuss about it now?
> >>
> >>nand-ecc-strength : integer ECC required strength.
> >>nand-ecc-size : integer step size associated to the ECC strength.
> > I'm okay with eit
On 05/02/2014 12:15, Grant Likely wrote:
On Wed, 29 Jan 2014 14:53:32 -0300, Ezequiel Garcia
wrote:
On Wed, Jan 29, 2014 at 03:34:13PM +0100, Boris BREZILLON wrote:
nand-ecc-level property statically defines NAND chip's ECC requirements.
Signed-off-by: Boris BREZILLON
---
Document
On Wed, 29 Jan 2014 14:53:32 -0300, Ezequiel Garcia
wrote:
> On Wed, Jan 29, 2014 at 03:34:13PM +0100, Boris BREZILLON wrote:
> > nand-ecc-level property statically defines NAND chip's ECC requirements.
> >
> > Signed-off-by: Boris BREZILLON
> > ---
> >
Hello Ezequiel
Le 29/01/2014 18:53, Ezequiel Garcia a écrit :
On Wed, Jan 29, 2014 at 03:34:13PM +0100, Boris BREZILLON wrote:
nand-ecc-level property statically defines NAND chip's ECC requirements.
Signed-off-by: Boris BREZILLON
---
Documentation/devicetree/bindings/mtd/nand.txt |
On Wed, Jan 29, 2014 at 03:34:13PM +0100, Boris BREZILLON wrote:
> nand-ecc-level property statically defines NAND chip's ECC requirements.
>
> Signed-off-by: Boris BREZILLON
> ---
> Documentation/devicetree/bindings/mtd/nand.txt |3 +++
> 1 file changed, 3 insertio
nand-ecc-level property statically defines NAND chip's ECC requirements.
Signed-off-by: Boris BREZILLON
---
Documentation/devicetree/bindings/mtd/nand.txt |3 +++
1 file changed, 3 insertions(+)
diff --git a/Documentation/devicetree/bindings/mtd/nand.txt
b/Documentation/devic
ecc level for the given device_node
+ * @np:Pointer to the given device_node
+ * @strengh: ECC strength
+ * @blk_size: ECC block size
+ *
+ * The function gets ecc level requirements from property 'nand-ecc-level'.
+ * Return 0 on success, -errno otherwise.
+ */
+int of_get_nand
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